C8051F537-IT Silicon Laboratories Inc, C8051F537-IT Datasheet - Page 20

IC 8051 MCU 2K FLASH 20TSSOP

C8051F537-IT

Manufacturer Part Number
C8051F537-IT
Description
IC 8051 MCU 2K FLASH 20TSSOP
Manufacturer
Silicon Laboratories Inc
Series
C8051F53xr
Datasheets

Specifications of C8051F537-IT

Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.25 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
336-1401

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F537-IT
Manufacturer:
Silicon Labs
Quantity:
135
C8051F52x/F52xA/F53x/F53xA
1.3. On-Chip Memory
The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data
RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general
purpose RAM, and direct addressing accesses the 128 byte SFR address space. The lower 128 bytes of
RAM are accessible via direct and indirect addressing. The first 32 bytes are addressable as four banks of
general purpose registers, and the next 16 bytes can be byte addressable or bit addressable.
Program memory consists of 7680 bytes (’F520/0A/1/1A and ’F530/0A/1/1A), 4 kB (’F523/3A/4/4A and
C8051F53x/53xA), or 2 kB (’F526/6A/7/7A and ’F536/6A/7/7A) of Flash. This memory is byte writable and
erased in 512-byte sectors, and requires no special off-chip programming voltage.
20
0x1DFF
0x0FFF
0x1E00
0x07FF
0x0000
0x1000
0x0000
0x0800
0x0000
PROGRAM/DATA MEMORY
'F520/0A/1/1A and 'F530/0A/1/1A
'F523/3A/4/4A and 'F533/3A/4/4A
'F526/6A/7/7A and 'F536/6A/7/7A
Programmable in 512
Programmable in 512
Programmable in 512
Byte Sectors)
Byte Sectors)
Byte Sectors)
RESERVED
RESERVED
RESERVED
(In-System
(In-System
(In-System
8 kB Flash
4 kB Flash
2 kB Flash
(Flash)
Figure 1.6. Memory Map
0xFF
0x7F
0x2F
0x1F
0x80
0x30
0x20
0x00
Rev. 1.3
(Indirect Addressing
(Direct and Indirect
INTERNAL DATA ADDRESS SPACE
General Purpose
Upper 128 RAM
Bit Addressable
Addressing)
Registers
Only)
DATA MEMORY (RAM)
(Direct Addressing Only)
Special Function
Lower 128 RAM
(Direct and Indirect
Addressing)
Register's

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