C8051F537-IT Silicon Laboratories Inc, C8051F537-IT Datasheet - Page 191

• Manufacturer Part Number: C8051F537-IT
• Description: IC 8051 MCU 2K FLASH 20TSSOP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F53xr

Specifications of C8051F537-IT

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.25 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 336-1401

18.2.3. External Capture Mode
Capture Mode allows the external oscillator to be measured against the system clock. Timer 2 can be
clocked from the system clock, or the system clock divided by 12, depending on the T2ML (CKCON.4) and
T2XCLK bits. When a capture event is generated, the contents of Timer 2 (TMR2H:TMR2L) are loaded
into the Timer 2 reload registers (TMR2RLH:TMR2RLL) and the TF2H flag is set. A capture event is gener-
ated by the falling edge of the clock source being measured, which is the external oscillator/8. By recording
the difference between two successive timer capture values, the external oscillator frequency can be
determined with respect to the Timer 2 clock. The Timer 2 clock should be much faster than the capture
clock to achieve an accurate reading. Timer 2 should be in 16-bit auto-reload mode when using Capture
Mode.
For example, if T2ML = 1b and TF2CEN = 1b, Timer 2 will clock every SYSCLK and capture every external
clock divided by 8. If the SYSCLK is 24.5 MHz and the difference between two successive captures is
5984, then the external clock frequency is:
This mode allows software to determine the external oscillator frequency when an RC network or capacitor
is used to generate the clock source.
External Osc. / 8
SYSCLK / 12
Figure 18.6. Timer 2 Capture Mode Block Diagram
T2XCLK
1
0
24.5 MHz
------------------------
SYSCLK

5984 8 
M
H
T
3
M
T
3
L
C8051F52x/F52xA/F53x/F53xA
CKCON
M

T
2
H
External Osc. / 8
TF2CEN
M
T
2
L
1
0
=
M
T
1
M
T
0
0.032754 MHz or 32.754 kHz
S
C
A
1
S
C
A
0
TR2
Rev. 1.3
Capture
TCLK
TMR2RLH
TMR2H
TMR2RLL
TMR2L
TF2CEN
TR2CLK
TF2LEN
T2XCLK
TF2H
TF2L
TR2
Interrupt
191