STEVAL-IPE010V1 STMicroelectronics, STEVAL-IPE010V1 Datasheet
STEVAL-IPE010V1
Specifications of STEVAL-IPE010V1
Related parts for STEVAL-IPE010V1
STEVAL-IPE010V1 Summary of contents
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Features ■ Supports 1 3-phase WYE and Delta services, from wires ■ Computes cumulative active and reactive wide- band and fundamental harmonic energies ■ Computes active and reactive energies, RMS and momentary voltage and current ...
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Contents Contents 1 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STPMC1 9.10.4 9.11 Energy to frequency conversion (configuration bits: APL, KMOT, LVS, FUND ...
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Contents 10.4 Energy integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STPMC1 List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of figures List of figures Figure 1. STPMC1 device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STPMC1 1 Functional block diagram Figure 1. STPMC1 device block diagram VDD VDD VCC VCC Linear Vregs Linear Vregs Band Gap Band Gap BIAS BIAS XTAL1 XTAL1 Clock Clock Generator Generator XTAL2 XTAL2 CLK CLK DAx-C DAx DAx ...
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Pin configuration 2 Pin configuration Figure 2. Pin connections (top view) Table 2. Pin description Pin n° Symbol Type 1 MON MOP SCS ...
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STPMC1 3 Maximum ratings Table 3. Absolute maximum ratings Symbol V DC input voltage CC I Current on any pin (sink/source) PIN V Input voltage at all pins ID V Input voltage at OTP pin OTP ESD Human body model ...
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Functions 4 Functions Table 5. Programmable pin functions Programmable pin Standalone mode (APL = MON Output for stepper node (MB) - charge pump MOP Output for stepper node (MA) - charge pump LED 3-phase energy pulsed output ...
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STPMC1 5 Application Figure 3. Application schematic in standalone operating mode Current Current Sensor Sensor STPMS1 STPMS1 Voltage Voltage Sensor Sensor Current Current Sensor Sensor STPMS1 STPMS1 Voltage Voltage Sensor Sensor Current ...
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Application Table 6. Typical external components Function Reads or writes to a calculator device via SPI and performs computation Measurement reference clock Interface R-phase voltage, current Interface S-phase voltage, current Interface T-phase voltage, current Interface PTAT, neutral current Interface PTAT ...
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STPMC1 6 Electrical characteristics ( °C, 100 nF across unless otherwise specified) Table 7. Electrical characteristics Symbol Parameter Energy measurement accuracy f Effective bandwidth BW General Section ...
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Electrical characteristics Table 7. Electrical characteristics (continued) Symbol Parameter Crystal oscillator V Input high voltage IH V Input low voltage IL I Input current on XTAL2 in R External resistor p C External capacitors p f Nominal output frequency XTAL1 ...
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STPMC1 7 Terminology 7.1 Measurement error The error associated with the energy measured by the STPMC1 is defined as: 7.2 Conventions The lowest analog and digital power supply voltage is called V system ground (GND). All voltage specifications for digital ...
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Terminology 7.3 Notation Table 8. Notation Label u Voltage i Current u Phase X voltage ( Phase X current ( Neutral current N U Phase X RMS voltage ...
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STPMC1 8 Typical performance characteristics Figure 5. Supply current vs. supply voltage 7,5 7 6,5 6 5,5 5 4,5 4 Figure 6. Digital voltage regulator: line - ...
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Typical performance characteristics Figure 7. Gain response of decimator 18/77 Flat band (10Hz – 300Hz) Flat band (10Hz – 300Hz) Flat band (10Hz Flat band (10Hz 3 dB band (4Hz –700Hz band (4Hz –700Hz band (4Hz ...
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... The STPMC1 (also called a calculator ASSP designed for effective measurement in power line systems utilizing the Rogowski coil, current transformer, Shunt or Hall current sensors. This device, used with the STMicroelectronics STPMSx companion chip (an analog front-end device), can be implemented as standalone peripheral in a microprocessor based 1 3-phase energy meter. ...
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Theory of operation These four multiplexed signals are separated digital de-multiplexer, back into eight signals, called streams. The signal coming from the voltage channel of the STPMSx is named with the suffix V, while the stream coming from ...
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STPMC1 The calculator, thanks to its flexibility, can work in all worldwide distribution network standards. By programming the SYS OTP bits possible to implement the following systems: ● 3-phase, 4-wire RSTN, 4-system RSTN (tamper); ● 3-phase, 4-wire RSTN, ...
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Theory of operation source for the linear regulator. Also, this module produces several bias currents and voltages for all other analog modules and for the OTP module. Resetting the STPMC1 (status bit HLT) 9.3 The STPMC1 has no reset pin. ...
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STPMC1 The clock generator is responsible for two tasks. The first is to retard the turn-on of some functional blocks after POR in order to help a smooth start of external power supply circuitry by keeping off all major loads. ...
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Theory of operation ZCR signal Figure 9. Period and line voltage measurement (status bits: LIN, BFR, 9.6 LOW, BFF) From voltage channels, a base frequency signal LIN is obtained, which is high when the line voltage is rising and it ...
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STPMC1 Figure 10. LIN and BFR behavior when f The in-band base frequency resets the flag BFR. If BFR is cleared, the measured period value is latched, otherwise a default value of period is used as a stable data to ...
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Theory of operation The SWM mode is indicated by status bit NAH =0: ● Bit NAH=0 (SWM on) happens when BFR=1 and RMS value of current signal /4096 = 16 (I Xmax is big enough ...
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STPMC1 The no-load condition occurs when the product between U a given value. This value can be set by the LTCH configuration bits. Four different no-load threshold values can be chosen according to the two LTCH bits as reported in ...
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Theory of operation The other error condition occurs if the MOP, MON and LED pin outputs signals are different from the internal signals that drive them. This can occur if some of this pin is forced to GND or to ...
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STPMC1 Bit BCS is set according to Table 14. Tamper conditions BCS SYS = ∑ ...
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Theory of operation Figure 11. Currents of the three phase system in example The value I MAX register (internal value FFFF function of the sensor type, sensitivity and of the current channel gain. Let us suppose that ...
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STPMC1 Example 6: 3-ph system - BCS = 1 Let us consider a three-phase, four wires system where 3 The tamper ...
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Theory of operation Whatever the SYS bits setting (indicating phases presence and configuration), bit BSF is always calculated, but it is valid only in cases SYS and 3. In fact in this case all the three ...
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STPMC1 EMI tamper condition is not available as internal status signal, but it is available (in OR with other tamper conditions) on the SDATD pin of the device. In peripheral application mode it is possible to detect EMI tamper comparing ...
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Theory of operation Example 10: energy registers LSB value for SYS = 64000 pulses/kWh = 17.7 Hz* 15.258 *10 15.258 ...
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STPMC1 Table 17. LED pin configuration for APL = 0 LVS (1 bit) FUND (1 bit) KMOT (2 bits the number of pulses per kWh set with calibration. APL ...
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Theory of operation From signal P (3-ph active energy), stepper motor driving signals MA and MB (see Figure 12 ) are generated by means of internal divider, mono-flop and decoder and brought to MOP and MON pins. Figure 12. Stepper ...
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STPMC1 Table 20. LED pin configuration for APL = 2, 3 APL (2 bits) KMOT (2 bits 9.14 Negative power accumulation (configuration bit ABS, status bit SIGN) The ABS bits govern energy accumulation in case of negative power; ...
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Theory of operation Figure 13. Phase delay The ACR, ACS and ACT registers (bits [7:0], see paragraph 9.17.7) holds the information needed for this calculation. Let us indicate t RS Equation ...
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STPMC1 Example 12: Phase delay calculation MHz; MDIV = 0; FR1 = 0 XTAL1 LINE ACR[7:0] = 0101 1010 ACS[7:0] = 0010 0000 ACT[7:0] = 0000 0101 Asr[12 Asr[10:0] = 000 ...
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Theory of operation 9.16 Calibration (configuration bits: PM, TCS, CIX, CVX, CCA, CCB, CPX) 9.16.1 Voltage and current channels calibration The 8-bit calibration values CVX and CIX (where X stands for are used as static ...
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STPMC1 Equation 4 is the phase compensation in degree, phc K is the calculated coefficient, PHC f is the frequency of voltage signal, line f is the clock for phase compensation. phc The clock for phase compensation f Table 22. ...
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Theory of operation Example 14: Phase compensation for TCS = 0 Phase shift current for - CPC[ (16 CPC[0] + CPX[3:0]) phc Phase shift current for CPC[ ...
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STPMC1 Example 15: Phase compensation for TCS = 1 Phase shift current for - CPC[ CPX[ (32 CpC[1: CPC[0] + CPX[3:0]) phc Phase shift current for CPC[1] ...
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Theory of operation Example 16: Phase compensation for Phase shift current for - CPC[ CPX[ (32 CpC[1: CPC[0] + CPX[3:0]) phc Phase shift current for CPC[1] = ...
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STPMC1 An asymmetrical compensation is implemented by multiplying the phase current with the neutral current with respectively, as shown below: Table 27. Mutual current compensation matrix for single-phase systems (SYS > 3) phase ...
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Theory of operation 9.17 Data records map There are seven groups of four data records available, each consisting of a parity ...
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STPMC1 0.4 PRD: ● period: 12-bit line period measurement (see paragraph from R-phase signal missing from S-phase then from T-phase. The value of the period can be calculated from the decimal value of period as: Equation 10 ...
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Theory of operation Equation 11 ● iN MOM: 16-bit momentary value of neutral current Note: In systems 3-phase, no neutral, u 9.17.3 Group 2 data records Figure 16. Group 2 data records parity parity parity parity parity parity DER DER ...
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STPMC1 9.17.4 Group 3 data records Figure 17. Group 3 data records parity parity parity parity parity parity DAR DAR DAR DAR DAS DAS DAS DAS parity parity parity parity parity parity DAT DAT DAT DAT parity parity parity parity ...
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Theory of operation 9.17.5 Group 4 data records Figure 18. Group 4 data records parity parity parity parity parity parity DRR DRR DRR DRR DRS DRS DRS DRS parity parity parity parity parity parity DRT DRT DRT DRT parity parity ...
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STPMC1 9.17.6 Group 5 data records Figure 19. Group 5 data records parity parity parity parity parity parity DFR DFR DFR DFR DFS DFS DFS DFS parity parity parity parity parity parity DFT DFT DFT DFT parity parity parity parity ...
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Theory of operation 9.17.7 Group 6 data records Figure 20. Group 6 data records parity parity parity parity parity parity ACR ACR ACR ACR ACS ACS ACS ACS parity parity parity parity parity parity ACT ACT ACT ACT parity parity ...
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STPMC1 Example 17: Parity calculation Let us calculate parity of DMR, the first register of second group: DMR: 02 prty = grp = 1 prty ^= * prty ^= *(bp+ prty ^= *(bp+ prty ...
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Theory of operation Table 30. X-phase status bits description Bit Name 0 BIL No-load Condition not detected 1 BCF signals alive 2 BFR Frequency of phase voltage is in range 3 SIGN Active energy is negative 4 LIN Phase 0 ...
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STPMC1 Each configuration bit can be written sending a byte command to STPMC1 through its SPI interface. See paragraph A system signal WE (see paragraph some OTP bit. There is also a special high voltage input pad VOTP, which delivers ...
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Theory of operation Table 31. Configuration bits map (continued) Address Name 7-BIT DEC Binary 0001000 8 ART 0001001 9 MSBF 0001010 10 ABS 0001011 11 0001100 12 LTCH 0001101 13 0001110 14 KMOT 0001111 15 0010000 16 LVS 0010001 17 ...
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STPMC1 Table 31. Configuration bits map (continued) Address Name 7-BIT DEC Binary 0010101 21 PM 0010110 22 FR1 0010111 23 0011000 24 0011001 25 0011010 26 0011011 27 CCA 0011100 28 0011101 29 0011110 30 0011111 31 0100000 32 0100001 ...
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Theory of operation Table 31. Configuration bits map (continued) Address Name 7-BIT DEC Binary 1000000 64 1000001 65 1000010 66 1000011 67 CVR 1000100 68 1000101 69 1000110 70 1000111 71 1001000 72 1001001 73 1001010 74 1001011 75 CVS ...
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STPMC1 Table 31. Configuration bits map (continued) Address Name 7-BIT DEC Binary 1101110 110 ENH 1101111 111 CHK 9.20 Mode signals The STPMC1 includes 12 Mode signals located in the DRP and DFP registers, some are used for internal testing ...
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Theory of operation to boost the needed to program the OTP antifuse elements. WE (write Enable): This mode signal is used to permanently write to the OTP antifuse element. When this bit is not set, any write ...
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STPMC1 the SCS status. If SCS is low, SCLNCL is the input of serial bit synchronization clock signal. When SCS is high, SCLNLC determines idle state of the SPI. SDATD : is the data pin. If SCS is low, the ...
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Theory of operation 9.21.2 Reading data records Data record reading takes place most often when there is an on-board microcontroller in an application. This microcontroller is capable of reading all measurement results and all system signals (configuration, calibration, status, mode). ...
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STPMC1 The first read out byte of the data record is the least significant byte (LSB) of the data value and of course, the fourth byte is the most significant byte (MSB) of the data value. Each byte can be ...
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Theory of operation Table 33. Functional description of commands Bit pos. 76543210 D0000000 CFG000=D, (shadow of first configurator, TSTD) DAAAAAAA CFGa=D, D1101111 CFG111=D, (shadow of last configurator, CHK) Example 18: Setting a configuration bit To set the configuration bit 47 ...
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STPMC1 t : data value is placed in SDA SDA value is stable and shifted into the device 4 −> (> 10 µs): writing clock period 3 5 −> bit data ...
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Theory of operation 1. collect all addresses of CFG bits to be permanently set into some list 2. clear all OTP shadow latches 3. set the system signal RD 4. connect a current source of at least + ...
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STPMC1 10 Energy calculation algorithm For the purpose of simplicity the energy computation shown below is relative to only one phase. Given line voltage and current as: Equation sin ( t) The voltage divider, AD converter ...
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Energy calculation algorithm In case of shunt sensor (TCS = 1), an additional stage of internal digital differentiated produces the value: Equation / The shunt preamplifier, AD converter and calibrator produce the ...
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STPMC1 In case of a non Rogowski sensor, the corresponding products are: Equation Equation Then a subtraction ...
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Energy calculation algorithm multiplied by the 16-bit current stream from the yielding: Equation ABk 1 uiic i Equation INT ui ...
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STPMC1 10.3 Voltage and current RMS values calculation The I value is produced from 16-bit value of RMS Equation ∫ RMS L INT T 0 The Ui is produced from stream and 16-bit ...
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Energy calculation algorithm The DSP performs also an integration of powers (P, Q) into energies: Equation RMS RMS Equation RMS RMS These integrators are implemented as up/down counters and they ...
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STPMC1 11 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: ® ...
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Package mechanical data Dim. Min 0.05 A2 0.8 b 0.19 c 0.09 D 6.4 E 6 0° PIN 1 IDENTIFICATION 1 74/77 TSSOP20 mechanical data mm. Typ. Max. ...
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STPMC1 Tape & reel TSSOP20 mechanical data Dim. Min 12 6.8 Bo 6.9 Ko 1.7 Po 3.9 P 11.9 mm. Typ. Max. Min. 330 13.2 0.504 0.795 2.362 22.4 7 0.268 7.1 ...
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Revision history 12 Revision history Table 34. Document revision history Date Revision 22-May-2009 1 03-Jul-2009 2 28-Jul-2009 3 19-May-2010 4 76/77 Initial release. Updated: paragraphs 9.4 , 9.16 and Updated: paragraph 9.16.2 . Added: Example 5: 3-ph system - BCS ...
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... STPMC1 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...