PIC18F26K22-I/ML Microchip Technology, PIC18F26K22-I/ML Datasheet - Page 219

• Manufacturer Part Number: PIC18F26K22-I/ML
• Description: IC PIC MCU 64KB FLASH 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F26K22-I/ML

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 19x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad
• Controller Family/series: PIC18
• No. Of I/o's: 25
• Eeprom Memory Size: 1KB
• Ram Memory Size: 3896Byte
• Cpu Speed: 64MHz
• No. Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.2.6
In SPI Master mode, module clocks may be operating
at a different speed than when in Full-Power mode; in
the case of the Sleep mode, all clocks are halted.
Special care must be taken by the user when the
MSSPx clock is much faster than the system clock.
In Slave mode, when MSSPx interrupts are enabled,
after the master completes sending data, an MSSPx
interrupt will wake the controller from Sleep.
If an exit from Sleep mode is not desired, MSSPx
interrupts should be disabled.
TABLE 15-1:
 2010 Microchip Technology Inc.
ANSELA
ANSELB
ANSELC
ANSELD
INTCON
IPR1
IPR3
PIE1
PIE3
PIR1
PIR3
PMD1
SSP1BUF
SSP1CON1
SSP1CON3
SSP1STAT
SSP2BUF
SSP2CON1
SSP2CON3
SSP2STAT
TRISA
TRISB
TRISC
TRISD
Legend:
Note 1: PIC18(L)F2XK22 devices.
Name
2: PIC18(L)F4XK22 devices.
SPI OPERATION IN SLEEP MODE
Shaded bits are not used by the MSSPx in SPI mode.
MSSP2MD MSSP1MD
GIE/GIEH
ACKTIM
ACKTIM
SSP2IP
SSP2IE
TRISA7
TRISB7
TRISC7
TRISD7
SSP2IF
ANSC7
ANSD7
WCOL
WCOL
Bit 7
SMP
SMP
REGISTERS ASSOCIATED WITH SPI OPERATION
—
—
—
—
—
PEIE/GIEL
BCL2IP
BCL2IE
SSPOV
SSPOV
TRISA6
TRISB6
TRISC6
TRISD6
ANSC6
ANSD6
BCL2IF
ADIP
ADIE
ADIF
PCIE
PCIE
Bit 6
CKE
CKE
—
—
TMR0IE
TRISA5
TRISB5
TRISC5
TRISD5 TRISD4
SSPEN
SSPEN
ANSA5
ANSB5
ANSC5
ANSD5
RC1IP
RC2IP
RC1IE
RC2IE
RC1IF
RC2IF
SCIE
SCIE
Bit 5
SSP1 Receive Buffer/Transmit Register
SSP2 Receive Buffer/Transmit Register
D/A
D/A
—
ANSD4
CCP5MD
TRISA4
TRISB4
TRISC4
ANSC4
Preliminary
ANSB4
INT0IE
TX1IP
TX2IP
TX1IE
TX2IE
BOEN
BOEN
TX1IF
TX2IF
Bit 4
CKP
CKP
—
P
P
(2)
(2)
TRISB3
TRISD3
ANSB3
ANSD3
CCP4MD
CTMUIP
CTMUIE
CTMUIF
SSP1IP
SSP1IE
TRISA3
TRISC3
ANSC3
SSP1IF
SDAHT
SDAHT
ANSA3
In SPI Master mode, when the Sleep mode is selected,
all module clocks are halted and the transmission/
reception will remain in that state until the device
wakes. After the device returns to Run mode, the
module will resume transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in Sleep mode and data
to be shifted into the SPI Transmit/Receive Shift
register. When all 8 bits have been received, the
MSSPx interrupt flag bit will be set and if enabled, will
wake the device.
RBIE
Bit 3
S
S
PIC18(L)F2X/4XK22
(1)
(2)
(1)
(2)
TRISB2
TMR5GIP
TMR5GIE
TMR5GIF
ANSB2
CCP3MD
CCP1IP
CCP1IE
TMR0IF
CCP1IF
TRISA2
TRISC2
TRISD2
ANSC2
ANSD2
SBCDE
SBCDE
ANSA2
Bit 2
R/W
R/W
SSPM<3:0>
SSPM<3:0>
(1)
(1)
TRISB1
TRISD1
TMR3GIP
TMR3GIE
TMR3GIF
ANSB1
ANSD1
CCP2MD
TMR2IP
TMR2IE
TMR2IF
TRISA1
TRISC1
ANSA1
INT0IF
AHEN
AHEN
Bit 1
UA
UA
—
(1)
(2)
(1)
(2)
TRISB0
TRISD0
ANSD0
TMR1GIP
TMR1GIE
TMR1GIF
ANSB0
CCP1MD
TMR1IP
TMR1IE
TMR1IF
TRISA0
TRISC0
ANSA0
DHEN
DHEN
Bit 0
RBIF
DS41412A-page 219
BF
BF
—
(1)
(2)
(1)
(2)
Register
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