PIC18F26K22-I/ML Microchip Technology, PIC18F26K22-I/ML Datasheet - Page 251

• Manufacturer Part Number: PIC18F26K22-I/ML
• Description: IC PIC MCU 64KB FLASH 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F26K22-I/ML

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 19x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad
• Controller Family/series: PIC18
• No. Of I/o's: 25
• Eeprom Memory Size: 1KB
• Ram Memory Size: 3896Byte
• Cpu Speed: 64MHz
• No. Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.6.13.1
During a Start condition, a bus collision occurs if:
a)
b)
During a Start condition, both the SDAx and the SCLx
pins are monitored.
If the SDAx pin is already low, or the SCLx pin is
already low, then all of the following occur:
• the Start condition is aborted,
• the BCLxIF flag is set and
• the MSSPx module is reset to its Idle state
The Start condition begins with the SDAx and SCLx
pins deasserted. When the SDAx pin is sampled high,
the Baud Rate Generator is loaded and counts down. If
the SCLx pin is sampled low while SDAx is high, a bus
collision occurs because it is assumed that another
master is attempting to drive a data ‘1’ during the Start
condition.
FIGURE 15-33:
 2010 Microchip Technology Inc.
(Figure 15-32).
SDAx or SCLx are sampled low at the beginning
of the Start condition (Figure 15-32).
SCLx is sampled low before SDAx is asserted
low (Figure 15-33).
SDAx
SCLx
SEN
BCLxIF
S
SSPxIF
Bus Collision During a Start
Condition
BUS COLLISION DURING START CONDITION (SDAx ONLY)
condition if SDAx = 1, SCLx = 1
Set SEN, enable Start
SDAx sampled low before
Start condition. Set BCLxIF.
S bit and SSPxIF set because
SDAx = 0, SCLx = 1.
SDAx goes low before the SEN bit is set.
S bit and SSPxIF set because
SDAx = 0, SCLx = 1.
Set BCLxIF,
Preliminary
SSPxIF and BCLxIF are
cleared by software
If the SDAx pin is sampled low during this count, the
BRG is reset and the SDAx line is asserted early
(Figure 15-34). If, however, a ‘1’ is sampled on the
SDAx pin, the SDAx pin is asserted low at the end of
the BRG count. The Baud Rate Generator is then
reloaded and counts down to zero; if the SCLx pin is
sampled as ‘0’ during this time, a bus collision does not
occur. At the end of the BRG count, the SCLx pin is
asserted low.
Note:
PIC18(L)F2X/4XK22
SEN cleared automatically because of bus collision.
SSPx module reset into Idle state.
The reason that bus collision is not a factor
during a Start condition is that no two bus
masters can assert a Start condition at the
exact same time. Therefore, one master
will always assert SDAx before the other.
This condition does not cause a bus colli-
sion because the two masters must be
allowed to arbitrate the first address fol-
lowing the Start condition. If the address is
the same, arbitration must be allowed to
continue into the data portion, Repeated
Start or Stop conditions.
SSPxIF and BCLxIF are
cleared by software
DS41412A-page 251