PI7C21P100BNHE Pericom Semiconductor, PI7C21P100BNHE Datasheet - Page 25

• Manufacturer Part Number: PI7C21P100BNHE
• Description: Peripheral Drivers & Components (PCIs) PCI-X to PCI-XBridge 2 Port
• Manufacturer: Pericom Semiconductor

Specifications of PI7C21P100BNHE

• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Package / Case: CSBGA-304
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.2.1.4
4.2.2
4.2.3
4.3
Table 4-3 READ TRANSACTIN HANDLING
PI7C21P100B attempts to transfer the write data on the PCI-X interface as soon as the
transaction ends or a 128-byte boundary is crossed. Writes greater than 128 bytes are possible
only if more than one 128-byte sector fills up before the write operation is issued on the PCI-
X interface.
When the originating bus is operating in the PCI-X mode and the destination bus is operating
in the conventional PCI mode, PI7C21P100B uses the PCI conventional memory write
command for both the PCI-X memory write and PCI-X memory write block commands.
PI7C21P100B attempts to transfer write data on the conventional PCI interface when the PCI-
X data crosses a 128-byte boundary or the end of the PCI-X transfer occurs. As long as a
128-byte buffer is full, or the end of transfer remains from the PCI-X memory write command
when a 128-byte boundary is crossed, the transfer will continue on the conventional PCI
interface.
DELAYED/SPLIT WRITE TRANSACTIONS
Delayed/Split write forwarding is used for I/O write transactions, Type 1 configuration write
transactions, and Type 0 configuration write transactions.
Delayed/Split write forwarding transactions are retried on the originating bus, completed on
the destination bus (if necessary), and then completed on the originating bus. For DWORD
transactions, PI7C21P100B uses delayed transactions in conventional PCI mode and split
requests in PCI-X mode. Only one request queue entry is allowed for either delayed or split
write transactions.
IMMEDIATE WRITE TRANSACTIONS
PI7C21P100B considers Type 0 configuration writes on the primary bus meant for the bridge
as immediate write transactions for the bridge. PI7C21P100B will execute the transaction and
indicate its completion by accepting the DWORD of data immediately.
READ TRANSACTIONS
Read transactions are treated as delayed read for conventional PCI mode, split read for PCI-X
mode, or immediate read. Table 4-3 shows the read behavior.
Memory Read
Memory Read Line
Memory Read Multiple
Memory Read DWORD (PCI-X mode)
Memory Read Block (PCI-X mode)
I/O Read
Type 0 Configuration Read
PCI-X TO PCI
Type of Transaction
Page 25 of 79
Delayed
Delayed
Delayed
Split (PCI-X mode)
Split (PCI-X mode)
Delayed/Split (PCI-X)
Immediate on the primary bus, Delayed/Split (PCI-X
mode) on the secondary bus
2-PORT PCI-X TO PCI-X BRIDGE
November 2005 – Revision 1.02
Type of Handling
PI7C21P100B