PI7C21P100BNHE Pericom Semiconductor, PI7C21P100BNHE Datasheet - Page 29

• Manufacturer Part Number: PI7C21P100BNHE
• Description: Peripheral Drivers & Components (PCIs) PCI-X to PCI-XBridge 2 Port
• Manufacturer: Pericom Semiconductor

Specifications of PI7C21P100BNHE

• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Package / Case: CSBGA-304
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.3.5.2
4.3.5.3
4.3.6
4.4
The method used for transfers in PCI-to-PCI mode is user defined in the primary and
secondary data buffering control registers. These registers have bits for memory read to
prefetchable space, memory read line, and memory read multiple transactions. For memory
read, the bits select whether to read a DWORD, read to a cache line boundary, or to fill the
prefetch buffer. For memory read line and memory read multiple transactions, the bits select
whether to read to a cache line boundary or to fill the prefetch buffer. In all cases, if the bits
are selected to fill the prefetch buffer, the maximum amount of data that is requested on the
target interface is controllable by the setting of the maximum memory read byte count bits of
the Primary and Secondary Data Buffering Control registers. When more than 512 bytes are
requested, the bridge fetches data to fill the buffer and then fetches more data to keep the
buffer filled as sectors (128 bytes) are emptied and become free to use again.
The method used for transfers in the PCI to PCI-X mode is similar to transfers in the PCI-to-
PCI mode, except that the maximum request amount may be additionally constrained by the
setting of the split transaction commitment limit value in the upstream or downstream split
transaction register. The only other difference is that prefetching will not stop when the
originating master disconnects. Prefetching will only stop when all of the requested data is
received.
DYNAMIC PREFETCH (CONVENTIONAL PCI MODE ONLY)
For prefetchable reads described in the previous section, the prefetching length is normally
predefined and cannot be changed once it is set. This may cause some inefficiency, as the
prefetching length determined could be larger or smaller than the actual data being prefetched.
To make prefetching more efficient, PI7C21P100B incorporates dynamic prefetching control
logic. This logic regulates the different PCI memory read commands (MR – memory read,
MRL – memory read line, and MRM – memory read multiple) to improve memory read burst
performance. PI7C21P100B tracks every memory read burst transaction and tallies the status.
By using the status information, PI7C21P100B can determine to increase, reduce, or keep the
same cache line length to be prefetched. Over time, PI7C21P100B can better match the
correct cache line setting to the length of data being requested. The dynamic prefetching
control logic is set with bits[3:2] offset 48h.
CONFIGURATION TRANSACTIONS
Configuration transactions are used to initialize a PCI system. Every PCI device
has a configuration space that is accessed by configuration commands. All registers are
accessible in configuration space only.
In addition to accepting configuration transactions for initialization of its own configuration
space, the PI7C21P100B also forwards configuration transactions for device initialization in
hierarchical PCI systems, as well as for special cycle generation.
PCI TO PCI
PCI TO PCI-X
Page 29 of 79
2-PORT PCI-X TO PCI-X BRIDGE
November 2005 – Revision 1.02
PI7C21P100B