PI7C21P100BNHE Pericom Semiconductor, PI7C21P100BNHE Datasheet - Page 35

• Manufacturer Part Number: PI7C21P100BNHE
• Description: Peripheral Drivers & Components (PCIs) PCI-X to PCI-XBridge 2 Port
• Manufacturer: Pericom Semiconductor

Specifications of PI7C21P100BNHE

• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Package / Case: CSBGA-304
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6
6.1
6.2
Table 5-1 SUMMARY OF TRANSACTION ORDERING IN PCI MODE
Table 5-2 SUMMARY OF TRANSACTION ORDERING IN PCI-X MODE
CLOCKS
This chapter provides information about the clocks.
PRIMARY AND SECONDARY CLOCK INPUTS
The primary and secondary interface on PI7C21P100B each has its own clock input pin.
P_CLK is the clock input for the primary and S_CLK is the input for the secondary (S_CLK
also controls the internal arbiter). The two clocks are independent of each other and may be
run synchronously or asynchronously to each other at any value supported by the PCI or PCI-
X specifications. Each interface utilizes a separate internal PLL (phase-locked loop) circuit
when running in PCI-X mode. In PCI mode, the PLL’s are bypassed, allowing for any clock
frequency from 0 to 66MHz. If the primary is running at 133MHz in PCI-X mode, then the
secondary is limited to a minimum frequency of 33MHz in conventional PCI mode.
CLOCK JITTER
PI7C21P100B tolerates a maximum of +/- 250ps of short term and long term jitter on the
clock inputs. Short term jitter is defined as the relationship between one clock edge to the
next subsequent clock edge for one clock cycle, and long term jitter is the same relationship
over many clock cycles.
Pass
Posted Write
Delayed Read Request
Delayed Write Request
Delayed Read Completion
Delayed Write Completion
1. If the relaxed ordering bit is set in PCI to PCI mode, or the enable relaxed ordering bit in the primary and/or
Pass
Posted Write
Delayed Read Request
Delayed Write Request
Delayed Read Completion
Delayed Write Completion
1. If the relaxed ordering bit is set in PCI-X to PCI-X mode, or the enable relaxed ordering bit in the primary and/or
secondary data buffering control registers is set in any other mode, read completions can pass memory writes.
2. Split Read Completions with the same sequence ID must remain in address order.
secondary data buffering control registers is set in any other mode, read completions can pass memory writes.
Posted Write
No
No
No
No
No
Memory
Write
No
No
No
No
No
1
1
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Delayed
Read
Request
Yes
Yes
Yes
Yes
Yes
Split Read
Request
Yes
Yes
Yes
Yes
Yes
Delayed
Write
Request
Yes
Yes
No
Yes
Yes
Split Write
Request
Yes
Yes
No
Yes
Yes
2-PORT PCI-X TO PCI-X BRIDGE
November 2005 – Revision 1.02
Delayed
Read
Completion
Yes
Yes
Yes
Yes
Yes
Split Read
Completion
Yes
Yes
Yes
Yes
Yes
2
PI7C21P100B
Delayed
Write
Completion
Yes
Yes
Yes
Yes
No
Split Write
Completion
Yes
Yes
Yes
Yes
No