PI7C21P100BNHE Pericom Semiconductor, PI7C21P100BNHE Datasheet - Page 39

• Manufacturer Part Number: PI7C21P100BNHE
• Description: Peripheral Drivers & Components (PCIs) PCI-X to PCI-XBridge 2 Port
• Manufacturer: Pericom Semiconductor

Specifications of PI7C21P100BNHE

• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Package / Case: CSBGA-304
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 7-1 DELAY TIMES FOR DE-ASSERTION OF S_RST#
Table 7-2 DE-ASSERTION OF S_RST#
this requirement is met. During this time delay period, the secondary bus mode and frequency
is determined through the programmable pull-up circuit. This process may include up to 80us
for the capacitive load on S_PCIXCAP to be charged. By the time the 100us timer expires,
the bus mode and frequency will have been determined. The S_RST# signal is then
de-asserted a minimum of ten secondary bus PCI clock cycles later.
When the secondary bus is operating in PCI-X mode, an internal PLL is used to source the
clock tree for the secondary clock domain inside PI7C21P100B. The appropriate range and
tuning bits for the PLL are set once the mode and frequency are determined, and an internal
PLL reset signal is deactivated to allow the PLL to begin locking to the S_CLK input
frequency. The PLL requires an allowance of 100us to accomplish this frequency lock. An
internal reset is held on the logic in the secondary clock domain until this time period has
elapsed. While the internal reset is active, PI7C21P100B will not respond to any secondary
bus transactions. When the secondary bus is operating in PCI mode, the internal PLL for the
secondary interface is not used. The internal PLL reset remains activated, keeping the PLL in
the bypass mode, and the internal logic reset is held for 5 additional secondary PCI clock
cycles.
T
T
T
T
Note: Primary and secondary clock cycles refer to clock cycles whose period is determined by the P_CLK and
S_CLK inputs.
PIRSTDLY
XCAP
SRSTDLY
SIRSTDLY
Conventional PCI
7 primary clock
cycles
6675 primary clock
cycles
11 secondary and 7
primary clock
cycles
16 secondary clock
cycles
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PCI-X 66
6678 primary clock
cycles
100us – 133us
6675 primary clock
cycles
100us – 133us
11 secondary and 7
primary clock
cycles
6687 secondary
clock cycles
100us – 133us
2-PORT PCI-X TO PCI-X BRIDGE
PCI-X 100
13350 primary
clock cycles
133us – 200us
13347 primary
clock cycles
133us – 200us
11 secondary and 7
primary clock
cycles
13350 secondary
clock cycles
133us – 200us
November 2005 – Revision 1.02
PCI-X 133
13350 primary
clock cycles
100us – 133us
13347 primary
clock cycles
100us – 133us
11 secondary and 7
primary clock
cycles
13350 secondary
clock cycles
100us – 133us
PI7C21P100B