PI7C21P100BNHE Pericom Semiconductor, PI7C21P100BNHE Datasheet - Page 57

Peripheral Drivers & Components (PCIs) PCI-X to PCI-XBridge 2 Port

PI7C21P100BNHE

Manufacturer Part Number
PI7C21P100BNHE
Description
Peripheral Drivers & Components (PCIs) PCI-X to PCI-XBridge 2 Port
Manufacturer
Pericom Semiconductor
Datasheet

Specifications of PI7C21P100BNHE

Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3 V to 3.6 V
Package / Case
CSBGA-304
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PI7C21P100BNHE
Manufacturer:
Pericom
Quantity:
135
Part Number:
PI7C21P100BNHE
Manufacturer:
PI
Quantity:
1 831
8.1.43
8.1.44
PRIMARY RETRY COUNTER REGISTER – OFFSET 60h
The below settings are the only allowed values. Other settings are not valid and will result in
smaller retry counts. When the counter expires, the bridge discards the requested transaction
on the primary bus and issues SERR# on the primary bus if enabled.
0000 0000: No expiration limit
8000 0000: Allow 2G retries before expiration
0100 0000: Allow 16M retries before expiration
0001 0000: Allow 64K retries before expiration
0000 0100: Allow 256 retries before expiration
SECONDARY RETRY COUNTER REGISTER – OFFSET 64h
BIT
0
BIT
31
30:25
24
23:17
16
15:9
8
7:0
BIT
31
30:25
24
23:17
16
15:9
8
7:0
FUNCTION
Secondary Retry Count
SERR# Disable
FUNCTION
2G Retry Count Control
RESERVED
16M Retry Count
Control
RESERVED
64K Retry Count
Control
RESERVED
256 Retry Count
Control
RESERVED
FUNCTION
2G Retry Count Control
RESERVED
16M Retry Count
Control
RESERVED
64K Retry Count
Control
RESERVED
256 Retry Count
Control
RESERVED
TYPE
TYPE
RO
RO
TYPE
RO
RO
RW
RW
RW
RW
RO
RW
RO
RW
RW
RW
RO
RW
RO
Page 57 of 79
DESCRIPTION
Secondary Retry Count SERR# Disable
0: Assert SERR# and update bit[30] offset 04h of the status register
if the secondary retry counter expires and bit[8] offset 04h in the
command register is set. Discard the transaction and set bit[0] offset
6Ch of the retry and timer status register.
1: Disable the assertion of SERR# if the primary retry counter
expires. Discard the transaction and set bit[0] offset 6Ch of the retry
and timer status register.
Reset to 0
DESCRIPTION
2G Retry Count Control
1: Designates 2G retries before expiration
Reset to 0
Reserved. Returns 000000 when read.
16M Retry Count Control
1: Designates 16M retries before expiration.
Reset to 0
Reserved. Returns 0000000 when read.
64K Retry Count Control
1: Designates 64K retries before expiration.
Reset to 0
Reserved. Returns 0000000 when read.
256 Retry Count Control
1: Designates 256 retries before expiration.
Reset to 0
Reserved. Returns 00000000 when read.
DESCRIPTION
2G Retry Count Control
1: Designates 2G retries before expiration
Reset to 0
Reserved. Returns 000000 when read.
16M Retry Count Control
1: Designates 16M retries before expiration.
Reset to 0
Reserved. Returns 0000000 when read.
64K Retry Count Control
1: Designates 64K retries before expiration.
Reset to 0
Reserved. Returns 0000000 when read.
256 Retry Count Control
1: Designates 256 retries before expiration.
Reset to 0
Reserved. Returns 00000000 when read.
2-PORT PCI-X TO PCI-X BRIDGE
November 2005 – Revision 1.02
PI7C21P100B

Related parts for PI7C21P100BNHE