LFXP2-8E-5FTN256I Lattice, LFXP2-8E-5FTN256I Datasheet - Page 125

• Manufacturer Part Number: LFXP2-8E-5FTN256I
• Description: FPGA - Field Programmable Gate Array 8K LUTs 201 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-8E-5FTN256I

• Number Of Macrocells: 8000
• Number Of Programmable I/os: 201
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 226304
• Number Of I /o: 201
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Package: 256FTBGA
• Family Name: LatticeXP2
• Device Logic Units: 8000
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 201
• Ram Bits: 226304
• Re-programmability Support: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 9-2 describes the structure of the secondary clocks and edge clocks.
Figure 9-2. LatticeXP2 Secondary Clocks and Edge Clocks (LFXP2-40)
Primary Clock Note
The CLKOP must be used as the feedback source to optimize PLL performance.
Most designers use PLLs for clock tree injection removal mode and the CLKOP should be assigned to a primary
clock. This is done automatically by the software unless otherwise specified by the user.
CLKOP can route only to CLK0 to CLK5, while CLKOS/CLKOK can route to all primary clocks (CLK0 TO CLK7).
When CLK6 or CLK7 is used as a primary clock and there is only one clock input to the DCS, the DCS is assigned
as a buffer mode by the software. Please see the DCS section of this document for detailed information.
Specifying Clocks in the Design Tools
If desired, designers can specify the clock resources, primary, secondary or edge to be used to distribute a given
clock source. Figure 9-3 illustrates how this can be done in the Pre-map Preference editor. Alternatively, the prefer-
ence file can be used, as discussed in Appendix C.
Primary-Pure and Primary-DCS
Primary Clock Net can be assigned to either Primary-Pure (CLK0 to CLK5) or Primary-DCS (CLK6 and CLK7).
Global Primary Clock and Quadrant Primary Clock
Global Primary Clock
If a primary clock is not assigned as a quadrant clock, the software assumes it is a global clock.
There are six Global Primary/Pure clocks and two Global Primary/DCS clocks available.
ECLK1
ECLK1
Secondary Clock
Secondary Clock
Secondary Clock
Secondary Clock
sysIO Bank 0
sysIO Bank 5
Region 2
Region 3
Region 4
Region 1
DSP Row
DSP Row
EBR Row
9-3
Secondary Clock
Secondary Clock
Secondary Clock
Secondary Clock
Region 5
Region 6
Region 7
Region 8
sysIO Bank 1
sysIO Bank 4
ECLK2
ECLK2
LatticeXP2 sysCLOCK PLL
Design and Usage Guide