LFXP2-8E-5FTN256I Lattice, LFXP2-8E-5FTN256I Datasheet - Page 161

• Manufacturer Part Number: LFXP2-8E-5FTN256I
• Description: FPGA - Field Programmable Gate Array 8K LUTs 201 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-8E-5FTN256I

• Number Of Macrocells: 8000
• Number Of Programmable I/os: 201
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 226304
• Number Of I /o: 201
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Package: 256FTBGA
• Family Name: LatticeXP2
• Device Logic Units: 8000
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 201
• Ram Bits: 226304
• Re-programmability Support: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
True Dual Port RAM (RAM_DP_TRUE) – EBR Based
The EBR blocks in the LatticeXP2 devices can be configured as True-Dual Port RAM or RAM_DP_TRUE. IPex-
press allows users to generate the Verilog-HDL, VHDL or EDIF netlists for the memory size as per design require-
ments.
IPexpress generates the memory module as shown in Figure 10-10.
Figure 10-10. True Dual Port Memory Module Generated by IPexpress
The generated module makes use of these EBR blocks or primitives. For memory sizes smaller than an EBR block,
the module will be created in one EBR block. When the specified memory is larger than one EBR block, multiple
EBR blocks can be cascaded in depth or width (as required to create these sizes).
In True Dual Port RAM mode, the input data and address for the ports are registered at the input of the memory
array. The output data of the memory is optionally registered at the output.
The various ports and their definitions for Single Port Memory are listed in Table 10-5. The table lists the corre-
sponding ports for the module generated by IPexpress and for the EBR RAM_DP_TRUE primitive.
Table 10-5. EBR-based True Dual Port Memory Port Definitions
ClockA, ClockB
ClockEnA, ClockEnB
AddressA, AddressB
DataA, DataB
QA, QB
WrA, WrB
ResetA, ResetB
—
Reset (or RST) resets only the input and output registers of the RAM. It does not reset the contents of the memory.
Chip Select (CS) is a useful port in the EBR primitive when multiple cascaded EBR blocks are required by the
memory. The CS signal forms the MSB for the address when multiple EBR blocks are cascaded. Since CS is a 3-
bit bus, it can cascade eight memories easily. However, if the memory size specified by the user requires more than
eight EBR blocks, the ispLEVER software automatically generates the additional address decoding logic, which is
implemented in the PFU external to the EBR blocks.
Generated Module
Port Name in
CLKA, CLKB
CEA, CEB
ADA[x1:0], ADB[x2:0]
DIA[y1:0], DIB[y2:0]
DOA[y1:0], DOB[y2:0]
WEA, WEB
RSTA, RSTB
CSA[2:0], CSB[2:0]
EBR Block Primitive
Port Name in the
AddressA
ClockEnA
DataInA
ClockA
ResetA
WrA
QA
Clock for PortA and PortB
Clock Enables for Port CLKA and CLKB
Output Data Port A and Port B
Write Enable Port A and Port B
Reset for Port A and Port B
Chip Selects for each port
Address Bus Port A and Port B
Input Data Port A and Port B
Dual Port Memory
EBR-based True
RAM_DP_TRUE
10-11
Description
LatticeXP2 Memory Usage Guide
ClockB
ClockEnB
ResetB
WrB
AddressB
DataInB
QB
Rising Clock Edge
Active State
Active High
Active High
Active High
—
—
—
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