LFXP2-8E-5FTN256I Lattice, LFXP2-8E-5FTN256I Datasheet - Page 140

• Manufacturer Part Number: LFXP2-8E-5FTN256I
• Description: FPGA - Field Programmable Gate Array 8K LUTs 201 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-8E-5FTN256I

• Number Of Macrocells: 8000
• Number Of Programmable I/os: 201
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 226304
• Number Of I /o: 201
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Package: 256FTBGA
• Family Name: LatticeXP2
• Device Logic Units: 8000
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 201
• Ram Bits: 226304
• Re-programmability Support: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Reset Behavior
Figure 9-15 illustrates the asynchronous RST behavior.
Figure 9-15. CLKDIV Reset Behavior
Release Behavior
The port, “Release” is used to synchronize the all outputs after RST is de-asserted. Figure 9-16 Illustrates the
release behavior.
Figure 9-16. CLKDIV Release Behavior
CLKI
RST
CDIV1
RELEASE
CDIV2
CDIV4
CDIV8
CLKI
RST
CDIV1
CDIV2
CDIV4
CDIV8
De-asserted RST
registered
RST asserted
asynchronously.
All clock outputs are
forced low.
Clock start counting
De-asserted RST is
registered.
9-18
After de-asserted RST is
registered all outputs start
toggling.
Release synchronizes
outputs
LatticeXP2 sysCLOCK PLL
Design and Usage Guide