LFXP2-8E-5FTN256I Lattice, LFXP2-8E-5FTN256I Datasheet - Page 184

• Manufacturer Part Number: LFXP2-8E-5FTN256I
• Description: FPGA - Field Programmable Gate Array 8K LUTs 201 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-8E-5FTN256I

• Number Of Macrocells: 8000
• Number Of Programmable I/os: 201
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 226304
• Number Of I /o: 201
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Package: 256FTBGA
• Family Name: LatticeXP2
• Device Logic Units: 8000
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 201
• Ram Bits: 226304
• Re-programmability Support: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 10-37. FIFO_DC with Output Registers, End of Data Read Cycle
And finally, if you select the option to enable the output register with RdEn, it still delays the data out by one clock
cycle (as compared to the non-pipelined FIFO_DC). The RdEn should also be high during that clock cycle, other-
wise the data takes an extra clock cycle when the RdEn is goes true.
Figure 10-38. FIFO_DC with Output Registers and RdEn on Output Registers
RPReset
RPReset
WrClock
RdClock
WrClock
RdClock
Almost
Almost
Almost
Almost
Empty
Empty
Empty
Empty
Reset
WrEn
RdEn
Reset
WrEn
RdEn
Data
Data
Full
Full
Full
Full
Q
Q
Data_N-4
Data_N-3
Invalid Q
10-34
Data_N-2
Invalid Data
Invalid Data
Data_1
Data_1
LatticeXP2 Memory Usage Guide
Data_N
Data_2
Data_3