LFXP2-8E-5FTN256I Lattice, LFXP2-8E-5FTN256I Datasheet - Page 86

FPGA - Field Programmable Gate Array 8K LUTs 201 I/O Inst on DSP 1.2V -5 Spd

LFXP2-8E-5FTN256I

Manufacturer Part Number
LFXP2-8E-5FTN256I
Description
FPGA - Field Programmable Gate Array 8K LUTs 201 I/O Inst on DSP 1.2V -5 Spd
Manufacturer
Lattice
Datasheet

Specifications of LFXP2-8E-5FTN256I

Number Of Macrocells
8000
Number Of Programmable I/os
201
Data Ram Size
226304
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FTBGA-256
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
226304
Number Of I /o
201
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
*
Operating Temperature
-40°C ~ 100°C
Package
256FTBGA
Family Name
LatticeXP2
Device Logic Units
8000
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
201
Ram Bits
226304
Re-programmability Support
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LFXP2-8E-5FTN256I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
FlashBAK Time (from EBR to Flash)
JTAG Port Timing Specifications
XP2-5
XP2-8
XP2-17
XP2-30
XP2-40
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Timing v. A 0.12
MAX
BTCP
BTCPH
BTCPL
BTS
BTH
BTRF
BTCO
BTCODIS
BTCOEN
BTCRS
BTCRH
BUTCO
BTUODIS
BTUPOEN
Symbol
Device
TCK Clock Frequency
TCK [BSCAN] clock pulse width
TCK [BSCAN] clock pulse width high
TCK [BSCAN] clock pulse width low
TCK [BSCAN] setup time
TCK [BSCAN] hold time
TCK [BSCAN] rise/fall time
TAP controller falling edge of clock to valid output
TAP controller falling edge of clock to valid disable
TAP controller falling edge of clock to valid enable
BSCAN test capture register setup time
BSCAN test capture register hold time
BSCAN test update register, falling edge of clock to valid output
BSCAN test update register, falling edge of clock to valid disable
BSCAN test update register, falling edge of clock to valid enable
EBR Density (Bits)
Over Recommended Operating Conditions
Over Recommended Operating Conditions
166K
221K
276K
387K
885K
Parameter
3-31
Time (Typ.)
1.5
1.5
1.5
2.0
3.0
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
Min.
25
40
20
20
10
50
8
8
Max.
10
10
10
25
25
25
25
Units
s
s
s
s
s
mV/ns
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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