UPD78F0535GB(T)-UEU-A NEC, UPD78F0535GB(T)-UEU-A Datasheet - Page 167
UPD78F0535GB(T)-UEU-A
Manufacturer Part Number
UPD78F0535GB(T)-UEU-A
Description
8BIT MCU, 60K FLASH, 3KB RAM, LQFP
Manufacturer
NEC
Datasheet
1.UPD78F0535GBT-UEU-A.pdf
(773 pages)
Specifications of UPD78F0535GB(T)-UEU-A
Controller Family/series
UPD78
No. Of I/o's
55
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
8
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
60KB
Oscillator Type
External, Internal
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6.6.4 Example of controlling internal low-speed oscillation clock
driven (240 kHz (TYP.)) if the watchdog timer operation has been enabled by the option byte.
6.6.5 Clocks supplied to CPU and peripheral hardware
of registers.
The internal low-speed oscillation clock cannot be used as the CPU clock.
Only the following peripheral hardware can operate with this clock.
• Watchdog timer
• 8-bit timer H1 (if f
In addition, the following operation modes can be selected by the option byte.
• Internal low-speed oscillator cannot be stopped
• Internal low-speed oscillator can be stopped by software
The internal low-speed oscillator automatically starts oscillation after a reset release, and the watchdog timer is
(1) Example of setting procedure when stopping the internal low-speed oscillation clock
(2) Example of setting procedure when restarting oscillation of the internal low-speed oscillation clock
Caution If “Internal low-speed oscillator cannot be stopped” is selected by the option byte, oscillation of
The following table shows the relation among the clocks supplied to the CPU and peripheral hardware, and setting
Remarks 1. XSEL:
Internal high-speed oscillation clock
Internal high-speed oscillation clock
X1 clock
External main system clock
Subsystem clock
<1> Setting LSRSTOP to 1 (RCM register)
<1> Clearing LSRSTOP to 0 (RCM register)
Clock Supplied to CPU
When LSRSTOP is set to 1, the internal low-speed oscillation clock is stopped.
When LSRSTOP is cleared to 0, the internal low-speed oscillation clock is restarted.
the internal low-speed oscillation clock cannot be controlled.
2. CSS:
3. MCM0: Bit 0 of MCM
4. EXCLK: Bit 7 of the clock operation mode select register (OSCCTL)
5. ×:
Table 6-4. Clocks Supplied to CPU and Peripheral Hardware, and Register Setting
RL
is selected as the count clock)
Bit 2 of the main clock mode register (MCM)
Bit 4 of the processor clock control register (PCC)
don’t care
Supplied Clock
Clock Supplied to Peripheral Hardware
X1 clock
External main system clock
Internal high-speed oscillation clock
X1 clock
External main system clock
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17260EJ6V0UD
XSEL
0
1
1
1
1
0
1
1
1
1
CSS
0
0
0
0
0
1
1
1
1
1
MCM0
×
0
0
1
1
×
0
1
0
1
EXCLK
×
0
1
0
1
×
0
0
1
1
167
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