UPD78F9222MC(T)-5A4-A NEC, UPD78F9222MC(T)-5A4-A Datasheet - Page 187

• Manufacturer Part Number: UPD78F9222MC(T)-5A4-A
• Description: 8BIT MCU, 4K FLASH, 256B RAM, 78F9222
• Manufacturer: NEC

Specifications of UPD78F9222MC(T)-5A4-A

• Controller Family/series: UPD78
• No. Of I/o's: 17
• Ram Memory Size: 256Byte
• Cpu Speed: 10MHz
• No. Of Timers: 4
• No. Of: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 4KB
• Oscillator Type: External, Internal

Notes 1. TXE6 is synchronized by the base clock (f
Caution
Figure 11-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (2/2)
2. RXE6 is synchronized by the base clock (f
3. If “reception as 0 parity” is selected, the parity is not judged. Therefore, bit 2 (PE6) of asynchronous
1. At startup, transmission operation is started by setting TXE6 to 1 after having set POWER6 to
operation, set TXE6 to 1 after having set TXE6 to 0 and one clock of the base clock (f
elapsed. If TXE6 is set to 1 before one clock of the base clock (f
circuit may not able to be initialized.
set RXE6 to 1 after having set RXE6 to 0 and one clock of the base clock (f
RXE6 is set to 1 before one clock of the base clock (f
be able to be initialized.
serial interface reception error status register 6 (ASIS6) is not set and the error interrupt does not
occur.
TXE6
RXE6
ISRM6
PS61
1, then setting the transmit data to TXB6 after having waited for one clock or more of the
base clock (f
TXE6 to 0.
CL6
SL6
0
1
0
1
0
0
1
1
0
1
0
1
0
1
Note 1
Note 2
Disable transmission (synchronously reset the transmission circuit).
Enable transmission
Disable reception (synchronously reset the reception circuit).
Enable reception
Character length of data = 7 bits
Character length of data = 8 bits
Number of stop bits = 1
Number of stop bits = 2
“INTSRE6” occurs in case of error (at this time, INTSR6 does not occur).
“INTSR6” occurs in case of error (at this time, INTSRE6 does not occur).
PS60
XCLK6
0
1
0
1
). When stopping transmission operation, set POWER6 to 0 after having set
Enabling/disabling occurrence of reception completion interrupt in case of error
CHAPTER 11 SERIAL INTERFACE UART6
Parity bit not output.
Output 0 parity.
Output odd parity.
Output even parity.
User’s Manual U16898EJ5V0UD
Specification of character length of transmit/receive data
Transmission operation
Specification of number of stop bits of transmit data
Enabling/disabling transmission
XCLK6
Enabling/disabling reception
XCLK6
) set by CKSR6. When re-enabling reception operation,
) set by CKSR6. When re-enabling transmission
XCLK6
) has elapsed, the reception circuit may not
Reception without parity
Reception as 0 parity
Judge as odd parity.
Judge as even parity.
XCLK6
) has elapsed, the transmission
Reception operation
XCLK6
Note 3
) has elapsed. If
XCLK6
) has
187