UPD78F9222MC(T)-5A4-A NEC, UPD78F9222MC(T)-5A4-A Datasheet - Page 214

• Manufacturer Part Number: UPD78F9222MC(T)-5A4-A
• Description: 8BIT MCU, 4K FLASH, 256B RAM, 78F9222
• Manufacturer: NEC

Specifications of UPD78F9222MC(T)-5A4-A

• Controller Family/series: UPD78
• No. Of I/o's: 17
• Ram Memory Size: 256Byte
• Cpu Speed: 10MHz
• No. Of Timers: 4
• No. Of: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 4KB
• Oscillator Type: External, Internal

(4) Permissible baud rate range during reception
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The permissible error from the baud rate at the transmission destination during reception is shown below.
Caution Make sure that the baud rate error during reception is within the permissible error range, by
As shown in Figure 11-25, the latch timing of the receive data is determined by the counter set by baud rate
generator control register 6 (BRGC6) after the start bit has been detected. If the last data (stop bit) meets this
latch timing, the data can be correctly received.
Assuming that 11-bit data is received, the theoretical values can be calculated as follows.
Maximum permissible
Minimum permissible
FL = (Brate)
Data frame length
Brate: Baud rate of UART6
k:
FL:
Margin of latch timing: 2 clocks
data frame length
data frame length
using the calculation expression shown below.
of UART6
Set value of BRGC6
1-bit data length
−
1
Figure 11-25. Permissible Baud Rate Range During Reception
Latch timing
Start bit
Start bit
Start bit
CHAPTER 11 SERIAL INTERFACE UART6
User’s Manual U16898EJ5V0UD
Bit 0
Bit 0
FL
Bit 0
Bit 1
Bit 1
Bit 1
1 data frame (11 × FL)
FLmin
FLmax
Bit 7
Bit 7
Bit 7
Parity bit
Parity bit
Parity bit
Stop bit
Stop bit
Stop bit