UPD78F9222MC(T)-5A4-A NEC, UPD78F9222MC(T)-5A4-A Datasheet - Page 44
UPD78F9222MC(T)-5A4-A
Manufacturer Part Number
UPD78F9222MC(T)-5A4-A
Description
8BIT MCU, 4K FLASH, 256B RAM, 78F9222
Manufacturer
NEC
Datasheet
1.UPD78F9222MCT-5A4-A.pdf
(414 pages)
Specifications of UPD78F9222MC(T)-5A4-A
Controller Family/series
UPD78
No. Of I/o's
17
Ram Memory Size
256Byte
Cpu Speed
10MHz
No. Of Timers
4
No. Of
RoHS Compliant
Core Size
8bit
Program Memory Size
4KB
Oscillator Type
External, Internal
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3.4.2 Short direct addressing
44
[Function]
[Operand format]
[Description example]
[Illustration]
The memory to be manipulated in the fixed space is directly addressed with the 8-bit data in an instruction word.
The fixed space where this addressing is applied is the 160-byte space FE80H to FF1FH (FE80H to FEFFH
(internal high-speed RAM) + FF00H to FF1FH (special function registers)) for the PD78F9221, or the 256-byte
space FE20H to FF1FH (FE20H to FEFFH (internal high-speed RAM) + FF00H to FF1FH (special function
registers)) for the PD78F9222.
The SFR area where short direct addressing is applied (FF00H to FF1FH) is a part of the total SFR area. In this
area, ports which are frequently accessed in a program and a compare register of the timer counter are mapped,
and these SFRs can be manipulated with a small number of bytes and clocks.
When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is cleared to 0. When it is at 00H to
1FH, bit 8 is set to 1. See [Illustration] below.
EQU DATA1 0FE90H ; DATA1 shows FE90H of a saddr area,
MOV FE90H, #50H
Effective
address
Identifier
saddrp
15
saddr
When 8-bit immediate data is 20H to FFH,
When 8-bit immediate data is 00H to 1FH,
7
1
1
Instruction code
1
saddr-offset
OP code
PD78F9221: Label or FE80H to FF1FH immediate data
PD78F9222: Label or FE20H to FF1FH immediate data
PD78F9221: Label or FE80H to FF1FH immediate data (even address only)
PD78F9222: Label or FE20H to FF1FH immediate data (even address only)
1
; When setting saddr to FE90H and the immediate data to 50H
1
1
1
1
0
1
CHAPTER 3 CPU ARCHITECTURE
0
1
1
0
8
User’s Manual U16898EJ5V0UD
1
0
0
1
1
1
= 1.
= 0.
Description
0
0
0
1
0
0
0
0
0
0
1
0
0
OP code
90H (saddr-offset)
50H (immediate data)
Short direct memory
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