PIC18F2320-E/SO Microchip Technology, PIC18F2320-E/SO Datasheet - Page 111

• Manufacturer Part Number: PIC18F2320-E/SO
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2320-E/SO

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.4
PORTD is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction register is TRISD. Setting a
TRISD bit (= 1) will make the corresponding PORTD
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISD bit (= 0)
will make the corresponding PORTD pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATD) is also memory mapped.
Read-modify-write operations on the LATD register read
and write the latched output value for PORTD.
All pins on PORTD are implemented with Schmitt Trig-
ger input buffers. Each pin is individually configurable
as an input or output.
Three of the PORTD pins are multiplexed with outputs
P1B, P1C and P1D of the Enhanced CCP module. The
operation of these additional PWM output pins is
covered in greater detail in Section 16.0 “Enhanced
Capture/Compare/PWM (ECCP) Module”.
FIGURE 10-11:
© 2007 Microchip Technology Inc.
Note:
Note:
PORTD, TRISD and LATD
Registers
PORTD is only available on PIC18F4X20
devices.
On a Power-on Reset, these pins are
configured as digital inputs.
PORTD/CCP1 Select
CCP Data Out
PSPMODE
RD LATD
Data Bus
WR LATD
or PORTD
RD PORTD
WR TRISD
PSP Read
RD TRISD
PSP Write
Note 1:
BLOCK DIAGRAM OF RD7:RD5 PINS
I/O pins have diode protection to V
TRIS Latch
Data Latch
D
D
CK
CK
Q
Q
Q
Q
PIC18F2220/2320/4220/4320
0
1
DD
and V
0
1
Q
SS
.
EN
PORTD can also be configured as an 8-bit wide micro-
processor port (Parallel Slave Port) by setting control
bit, PSPMODE (TRISE<4>). In this mode, the input
buffers are TTL. See Section 10.6 “Parallel Slave
Port” for additional information on the Parallel Slave
Port (PSP).
EXAMPLE 10-4:
EN
CLRF
CLRF
MOVLW
MOVWF
0
1
D
Note:
PORTD
LATD
0xCF
TRISD
1
0
When the enhanced PWM mode is used
with either dual or quad outputs, the PSP
functions of PORTD are automatically
disabled.
TTL Buffer
; Initialize PORTD by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
: Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs
V
N
V
Schmitt Trigger
Input Buffer
P
INITIALIZING PORTD
DD
SS
DS39599G-page 109
I/O pin
(1)