PIC18F2320-E/SO Microchip Technology, PIC18F2320-E/SO Datasheet - Page 221

• Manufacturer Part Number: PIC18F2320-E/SO
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2320-E/SO

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.7
Figure 19-3 shows the operation of the A/D converter
after the GO/DONE bit has been set and the
ACQT2:ACQT0 bits are cleared. A conversion is
started after the following instruction to allow entry into
Sleep mode before the conversion begins.
Figure 19-4 shows the operation of the A/D converter
after the GO/DONE bit has been set and the
ACQT2:ACQT0 bits are set to ‘010’ and selecting a
4 T
FIGURE 19-3:
FIGURE 19-4:
© 2007 Microchip Technology Inc.
(Holding capacitor continues
acquiring input)
Set GO/DONE bit
AD
1
acquisition time before the conversion starts.
T
CY
Set GO/DONE bit
A/D Conversions
Holding capacitor is disconnected from analog input (typically 100 ns)
T
Automatic
Acquisition
Time
ACQT
- T
2
AD
Conversion starts
Cycles
T
AD
3
1 T
A/D CONVERSION T
A/D CONVERSION T
AD
b9
4
2 T
(Holding capacitor is disconnected)
Conversion starts
AD
b8
1
3 T
AD
b9
b7
2
Next Q4: ADRESH/ADRESL are loaded, GO/DONE bit is cleared,
4 T
Next Q4: ADRESH:ADRESL are loaded, GO/DONE bit is cleared,
PIC18F2220/2320/4220/4320
AD
b8
b6
3
AD
AD
5 T
ADIF bit is set, holding capacitor is connected to analog input.
CYCLES (A
CYCLES (A
ADIF bit is set, holding capacitor is reconnected to analog input.
AD
b5
b7
4
6 T
AD
T
b4
5
b6
AD
7 T
Clearing the GO/DONE bit during a conversion will abort
the current conversion. The A/D Result register pair will
NOT be updated with the partially completed A/D
conversion sample. This means the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers).
After the A/D conversion is completed or aborted, a
2 T
be started. After this wait, acquisition on the selected
channel is automatically started.
Cycles
CQT
CQT
AD
Note:
b3
b5
AD
6
8
<2:0> = 000, T
<2:0> = 010, T
wait is required before the next acquisition can
T
AD
b2
b4
7
9 T
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
AD
b3
b1
8
10
T
AD
ACQ
b0
b2
ACQ
9
11
= 0)
= 4 T
10
b1
AD
DS39599G-page 219
b0
11
)