PIC18F2320-E/SO Microchip Technology, PIC18F2320-E/SO Datasheet - Page 130

• Manufacturer Part Number: PIC18F2320-E/SO
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2320-E/SO

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F2220/2320/4220/4320
13.2
The Timer2 module has an 8-bit Period register, PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon Reset.
FIGURE 13-1:
TABLE 13-1:
DS39599G-page 128
INTCON
PIR1
PIE1
IPR1
TMR2
T2CON
PR2
OSCCON
Legend:
Note 1:
Name
Timer2 Interrupt
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits clear.
Timer2 Module Register
Timer2 Period Register
GIE/GIEH PEIE/GIEL
PSPIF
PSPIE
PSPIP
Note 1: TMR2 register output can be software selected by the MSSP module as a baud clock.
IDLEN
F
Bit 7
OSC
—
/4
(1)
(1)
(1)
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
TIMER2 BLOCK DIAGRAM
IRCF2
ADIF
ADIE
ADIP
Bit 6
T2CKPS1:T2CKPS0
1:1, 1:4, 1:16
Prescaler
TMR0IE
IRCF1
RCIF
RCIE
RCIP
Bit 5
2
INT0IE
IRCF0
TXIE
TXIP
Bit 4
TXIF
Comparator
TMR2
PR2
SSPIF
SSPIE
SSPIP
OSTS
RBIE
Bit 3
13.3
The output of TMR2 (before the postscaler) is fed to the
Synchronous Serial Port module which optionally uses
it to generate the shift clock.
EQ
Reset
TMR0IF
CCP1IF
CCP1IE
CCP1IP
TOUTPS3:TOUTPS0
IOFS
Bit 2
Postscaler
1:1 to 1:16
Output of TMR2
Output
TMR2IF
TMR2IE
TMR2IP
INT0IF
TMR2
SCS1
Bit 1
4
(1)
TMR1IE
TMR1IP
TMR1IF
SCS0
Bit 0
RBIF
© 2007 Microchip Technology Inc.
bit TMR2IF
0000 000x 0000 000u
0000 0000 0000 0000
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
1111 1111 1111 1111
0000 qq00 0000 qq00
Sets Flag
POR, BOR
Value on
Value on
all other
Resets