PIC18F2320-E/SO Microchip Technology, PIC18F2320-E/SO Datasheet - Page 270

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PIC18F2320-E/SO

Manufacturer Part Number
PIC18F2320-E/SO
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,28PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F2320-E/SO

Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
PIC18F2220/2320/4220/4320
BNOV
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39599G-page 268
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
PC
If Overflow
If Overflow
No
Q1
Q1
PC
PC
Read literal
Read literal
operation
Branch if Not Overflow
[ label ] BNOV
-128 ≤ n ≤ 127
if Overflow bit is ‘0’,
(PC) + 2 + 2n → PC
None
If the Overflow bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is
then a two-cycle instruction.
1
1(2)
HERE
1110
No
Q2
Q2
‘n’
‘n’
=
=
=
=
=
address (HERE)
0;
address (Jump)
1;
address (HERE + 2)
0101
BNOV Jump
operation
Process
Process
Data
Data
No
Q3
Q3
n
nnnn
Write to PC
operation
operation
No
No
Q4
Q4
nnnn
BNZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
PC
If Zero
If Zero
No
Q1
Q1
PC
PC
Read literal
Read literal
operation
Branch if Not Zero
[ label ] BNZ
-128 ≤ n ≤ 127
if Zero bit is ‘0’,
(PC) + 2 + 2n → PC
None
If the Zero bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is
then a two-cycle instruction.
1
1(2)
HERE
1110
No
Q2
Q2
‘n’
‘n’
=
=
=
=
=
© 2007 Microchip Technology Inc.
address (HERE)
0;
address (Jump)
1;
address (HERE + 2)
0001
BNZ
operation
Process
Process
Data
Data
No
Q3
Q3
n
Jump
nnnn
Write to PC
operation
operation
No
No
Q4
Q4
nnnn

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