PIC18F2320-E/SO Microchip Technology, PIC18F2320-E/SO Datasheet - Page 254

• Manufacturer Part Number: PIC18F2320-E/SO
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2320-E/SO

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F2220/2320/4220/4320
23.5
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PIC
The user program memory is divided into five blocks.
One of these is a boot block of 512 bytes. The remain-
der of the memory is divided into four blocks on binary
boundaries.
FIGURE 23-5:
TABLE 23-3:
DS39599G-page 252
300008h
300009h
30000Ah
30000Bh
30000Ch
30000Dh
Legend:
®
devices.
File Name
Program Verification and
Code Protection
(PIC18F2220/4220)
Shaded cells are unimplemented.
Unimplemented
Unimplemented
Unimplemented
CONFIG5L
CONFIG5H
CONFIG6L
CONFIG6H
CONFIG7L
CONFIG7H
Boot Block
4 Kbytes
Read ‘0’s
Read ‘0’s
Read ‘0’s
Block 0
Block 1
SUMMARY OF CODE PROTECTION REGISTERS
MEMORY SIZE/DEVICE
CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2X20/4X20
WRTD
Bit 7
CPD
—
—
—
—
(PIC18F2320/4320)
Unimplemented
EBTRB
WRTB
Boot Block
Bit 6
CPB
8 Kbytes
Read ‘0’s
Block 0
Block 1
Block 2
Block 3
—
—
—
WRTC
Bit 5
—
—
—
—
—
000000h
0001FFh
000200h
0007FFh
000800h
000FFFh
001000h
0017FFh
001800h
001FFFh
002000h
1FFFFFh
Address
Range
Bit 4
Each of the five blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 23-5 shows the program memory organization
for 4 and 8-Kbyte devices and the specific code protec-
tion bit associated with each block. The actual locations
of the bits are summarized in Table 23-3.
—
—
—
—
—
—
EBTR3
WRT3
Bit 3
CP3
—
—
—
(Unimplemented Memory Space)
Block Code Protection
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
CP1, WRT1, EBTR1
CP2, WRT2, EBTR2
CP3, WRT3, EBTR3
Controlled By:
EBTR2
WRT2
Bit 2
CP2
—
—
—
© 2007 Microchip Technology Inc.
EBTR1
WRT1
Bit 1
CP1
—
—
—
EBTR0
WRT0
Bit 0
CP0
—
—
—