PIC18F2320-E/SO Microchip Technology, PIC18F2320-E/SO Datasheet - Page 281

• Manufacturer Part Number: PIC18F2320-E/SO
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2320-E/SO

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

INCFSZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
© 2007 Microchip Technology Inc.
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
No
No
No
PC
CNT
If CNT
PC
If CNT
PC
Q1
Q1
Q1
=
=
=
=
≠
=
register ‘f’
operation
operation
operation
Increment f, Skip if 0
[ label ]
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(f) + 1 → dest,
skip if result = 0
None
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is placed back in register ‘f’
(default).
If the result is ‘0’, the next
instruction which is already fetched
is discarded and a NOP is executed
instead, making it a two-cycle
instruction. If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
1
1(2)
Note: 3 cycles if skip and followed
HERE
NZERO
ZERO
Read
0011
No
No
No
Q2
Q2
Q2
Address (HERE)
CNT + 1
0;
Address (ZERO)
0;
Address (NZERO)
by a 2-word instruction.
INCFSZ
:
:
INCFSZ
11da
operation
operation
operation
Process
Data
No
No
No
Q3
Q3
Q3
ffff
f [,d [,a]]
CNT
destination
operation
operation
operation
Write to
PIC18F2220/2320/4220/4320
No
No
No
Q4
Q4
Q4
ffff
INFSNZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
No
No
No
PC
REG
If REG
PC
If REG
PC
Q1
Q1
Q1
=
=
≠
=
=
=
register ‘f’
operation
operation
operation
Increment f, Skip if Not 0
[ label ]
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(f) + 1 → dest,
skip if result ≠ 0
None
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is placed back in register ‘f’
(default).
If the result is not ‘0’, the next
instruction which is already fetched
is discarded and a NOP is executed
instead, making it a two-cycle
instruction. If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
1
1(2)
Note: 3 cycles if skip and followed
HERE
ZERO
NZERO
Read
0100
No
No
No
Q2
Q2
Q2
Address (HERE)
REG + 1
0;
Address (NZERO)
0;
Address (ZERO)
by a 2-word instruction.
INFSNZ
INFSNZ
10da
operation
operation
operation
Process
Data
No
No
No
Q3
Q3
Q3
DS39599G-page 279
REG
ffff
f [,d [,a]]
destination
operation
operation
operation
Write to
No
No
No
Q4
Q4
Q4
ffff