VS6624Q0KP STMicroelectronics, VS6624Q0KP Datasheet - Page 26
VS6624Q0KP
Manufacturer Part Number
VS6624Q0KP
Description
Display Modules & Development Tools CAMERA MODULE SINGLE CHIP 1.3MEGA
Manufacturer
STMicroelectronics
Datasheet
1.VS6624Q0KP.pdf
(106 pages)
Specifications of VS6624Q0KP
Description/function
Camera Module
Interface Type
Two-Wire Serial
Data Bus Width
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Data synchronization methods
8
Embedded codes
Prevention of false synchronization codes
Mode 1 (ITU656 compatible)
26/106
Data synchronization methods
External capture systems can synchronize with the data output from VL6624/VS6624 in one
of two ways:
1.
2.
Both methods of synchronization can be programmed to meet the needs of the host system.
The embedded code sequence can be inserted into the output data stream to enable the
external host system to synchronize with the output frames. The code consists of a 4-byte
sequence starting with 0xFF, 0x00, 0x00. The final byte in the sequence depends on the
mode selected.
Two types of embedded codes are supported by the VL6624/VS6624: Mode 1 (ITU656) and
Mode 2. The bSyncCodeSetup register is used to select whether codes are inserted or not
and to select the type of code to insert.
When embedded codes are selected each line of data output contains 8 additional clocks: 4
before the active video data and 4 after it.
The VL6624/VS6624 is able to prevent the output of 0xFF and/or 0x00 data from being
misinterpreted by a host system as the start of synchronization data. This function is
controlled the bCodeCheckEnable register.
The structure of an image frame with ITU656 codes is shown in
Synchronization codes are embedded in the output data
Via the use of two additional synchronization signals: VSYNC and HSYNC
Figure 11
.
VL6624/VS6624
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