VS6624Q0KP STMicroelectronics, VS6624Q0KP Datasheet - Page 32

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VS6624Q0KP

Manufacturer Part Number
VS6624Q0KP
Description
Display Modules & Development Tools CAMERA MODULE SINGLE CHIP 1.3MEGA
Manufacturer
STMicroelectronics
Datasheet

Specifications of VS6624Q0KP

Description/function
Camera Module
Interface Type
Two-Wire Serial
Data Bus Width
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Part Number:
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Data synchronization methods
Figure 16. QCLK options
Figure 17. Qualification clock
32/106
Bayer 10-Bit
Bayer 8-Bit
PCLK
YUV 4:0:0
RGB565
RGB444
YCbCr
Negative edge
Positive edge
Negative edge
Positive edge
The YUV, RGB and bayer timings are represented on
qualifying pclk clock. The output clock rate is effectively halved for the bayer 8-bit and
YUV4:0:0 modes where only one byte of output data is required per pixel.
data
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
PCLK
PCLK
PCLK
PCLK
PCLK
16-bit data output formats - 2 bytes per pixel
8-bit data output formats- 1 byte per pixel
Pix0_lsb
Pix0_lsb
Cb
n,n+1
D0
Pix0
Pix0
Pix0_msb
Pix0_msb
Y
n
D1
Pix1_lsb
Pix1_lsb
Cr
n,n+1
D2
Figure 17
Pix1
Pix1
Pix1_msb
Pix1_msb
Y
None-active
level - High
None-active
level - Low
, with the associated
n+1
Cb
VL6624/VS6624
Pix2_lsb
Pix2_lsb
n+2,n+3
Pix2
Pix2

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