VS6624Q0KP STMicroelectronics, VS6624Q0KP Datasheet - Page 33

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VS6624Q0KP

Manufacturer Part Number
VS6624Q0KP
Description
Display Modules & Development Tools CAMERA MODULE SINGLE CHIP 1.3MEGA
Manufacturer
STMicroelectronics
Datasheet

Specifications of VS6624Q0KP

Description/function
Camera Module
Interface Type
Two-Wire Serial
Data Bus Width
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
VS6624Q0KP/TR
Manufacturer:
ST
0
VL6624/VS6624
Master / Slave operation of PLCK
In normal operation VS6624 acts as a master. PCLK is independent of the input clock
frequency and does not have a determined phase relation to the input clock.
In SLAVE operation the input clock frequency is the same as the output clock frequency and
the output data is guaranteed with a certain phase relationship to the input clock. Internally,
the VS6624 uses clocks generated from the internal PLL, but a retiming stage is used to re-
sync the output to the input clock. In this output mode, derating is not possible.
Data synchronization methods
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