VS6624Q0KP STMicroelectronics, VS6624Q0KP Datasheet - Page 36

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VS6624Q0KP

Manufacturer Part Number
VS6624Q0KP
Description
Display Modules & Development Tools CAMERA MODULE SINGLE CHIP 1.3MEGA
Manufacturer
STMicroelectronics
Datasheet

Specifications of VS6624Q0KP

Description/function
Camera Module
Interface Type
Two-Wire Serial
Data Bus Width
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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0
Host communication - I²C control interface
10.2
Figure 20. Detailed overview of message format
36/106
SDA
SCL
repeated
condition
START
START
or
Sr
or
S
read. A read message is terminated by the bus master generating a negative acknowledge
after reading a final byte of data.
A message can only be terminated by the bus master, either by issuing a stop condition, a
repeated start condition or by a negative acknowledge after reading a complete byte during
a read operation.
Detailed overview of the message format
The V2W generic message format consists of the following sequence
(Sr)
S
1
MSB
Device Address
1
7-bit Device
Address
2
2
7
0 - Write
1 - Read
R/W
Bit
R/W
LSB
8
signal
slave
A
3
9
ACK
from
MSB
1
R/W=0 - Master
Data byte from
R/W=1 - Slave
2
transmitter
8-bit Data
4
7
LSB
8
receiver
signal
ACK
from
(A)
A
5
9
VL6624/VS6624
(Sr)
condition
repeated
P
6
STOP
Start
Sr
or
or
P
Sr
P

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