VS6624Q0KP STMicroelectronics, VS6624Q0KP Datasheet - Page 29

• Manufacturer Part Number: VS6624Q0KP
• Description: Display Modules & Development Tools CAMERA MODULE SINGLE CHIP 1.3MEGA
• Manufacturer: STMicroelectronics

Specifications of VS6624Q0KP

• Description/function: Camera Module
• Interface Type: Two-Wire Serial
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

VL6624/VS6624
Mode 2 Logical DMA channels
VSYNC and HSYNC
Horizontal synchronization signal (HSYNC)
The purpose of logical channels is to separate different data flows which are interleaved in
the data stream, in the case of the VS6624 this allows the identification of the pipe setup
bank used for an image frame. The DMA channel identifier number is directly encoded in the
4-byte mode2 embedded sync codes. The receiver can then monitor the DMA channel
identifier and de-multiplex the interleaved video streams to their appropriate DMA channel.
The bChannelID register can have the value 0 to 6. The DMA channel identifier must be fully
programmable to allow the host to configure which DMA channels the different video data
stream use.
●
The channel identifier is a part of Mode2 synchronization code, upper four bits of last byte of
synchronization code.
identifiers.
Figure 13. Mode 2 frame structure (VGA example)
The VL6624/VS6624 can provide two programmable hardware synchronization signals:
VSYNC and HSYNC. The position of these signals within the output frame can be
programmed by the user or an automatic setting can be used where the signals track the
active video portion of the output frame regardless of its size.
The HSYNC signal is controlled by the bHSyncSetup register. The following options are
available:
●
●
●
●
Logical channel control
enable/disable
select polarity
all lines or active lines only
manual or automatic
F
Figure 13.
F
32-bit embedded mode 2 sync code
DMA Channel Number
Valid channels = 0 to 6
Line code
0x0 = Line Start
0x1 = Line End
0x2 = Frame Start
0x3 = Frame End
0
illustrates the synchronization code with logical channel
0
0
Data synchronization methods
0
DC LC
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