VS6624Q0KP STMicroelectronics, VS6624Q0KP Datasheet - Page 31

• Manufacturer Part Number: VS6624Q0KP
• Description: Display Modules & Development Tools CAMERA MODULE SINGLE CHIP 1.3MEGA
• Manufacturer: STMicroelectronics

Specifications of VS6624Q0KP

• Description/function: Camera Module
• Interface Type: Two-Wire Serial
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

VL6624/VS6624
Pixel clock (PCLK)
Figure 15. VSYNC timing example
If manual mode is selected then the line number for VSYNC rising edge and falling edge is
programmable. The rising edge of VSYNC is programmed in the bVsyncRisingLine
registers, the pixel position for VSYNC rising edge is programmed in the bVsyncRisingPixel
registers. Similarly the line count for the falling edge position is specified in the
bVsyncFallingLine registers, and the pixel count is specified in the bVsyncFallingPixel
registers.
The PCLK signal is controlled by the
are available:
●
●
●
●
●
enable/disable
select polarity
select starting phase
qualify/don’t qualify embedded synchronization codes
enable/disable during horizontal blanking
BLANKING
BLANKING
ACTIVE
VIDEO
ACTIVE
VIDEO
Output formatter control
Data synchronization methods
register. The following options
vsync
V=1
V=0
V=1
V=0
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