ADSP-BF535PBBZ-200 Analog Devices Inc, ADSP-BF535PBBZ-200 Datasheet - Page 24

200/400MMAC 16-bit DSP MICROCOMPUTER

ADSP-BF535PBBZ-200

Manufacturer Part Number
ADSP-BF535PBBZ-200
Description
200/400MMAC 16-bit DSP MICROCOMPUTER
Manufacturer
Analog Devices Inc
Series
Blackfin®r
Type
Fixed Pointr

Specifications of ADSP-BF535PBBZ-200

Interface
PCI, SPI, SSP, UART, USB
Clock Rate
200MHz
Non-volatile Memory
External
On-chip Ram
308kB
Voltage - I/o
3.30V
Voltage - Core
1.50V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
260-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADSP-BF535PBBZ-200
Manufacturer:
Analog Devices Inc
Quantity:
10 000
ADSP-BF535
Clock and Reset Timing
Table 11
ABSOLUTE MAXIMUM RATINGS on Page
tions of CLKIN and clock multipliers must not select core and
system clocks in excess of 350/300/200 MHz and 133 MHz,
respectively.
Table 11. Clock and Reset Timing
1
2
3
4
Parameter
Timing Requirements
t
t
t
t
t
t
t
Switching Characteristics
t
Applies to Bypass mode and Non-bypass mode.
Applies after power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles, while
SSELx, MSELx and DF values can change from this point, but the values must be valid.
SSELx, MSELx and DF values must be held from this time, until the hold time expires.
CKIN
CKINL
CKINH
WRST
MSD
MSS
MSH
PFD
RESET is asserted, assuming stable power supplies and CLKIN (not including start-up time of external clock oscillator).
and
SSEL1–0
MSEL6–0
BYPASS
RESET
Figure 8
CLKIN
DF
CLKIN Period
CLKIN Low Pulse
CLKIN High Pulse
RESET Asserted Pulse Width Low
Delay from RESET Asserted to MSELx, SSELx, BYPASS,
and DF Valid
MSELx/SSELx/DF/BYPASS Stable Setup Before RESET
Deasserted
MSELx/SSELx/DF/BYPASS Stable Hold After RESET
Deasserted
Flag Output Disable Time After RESET Asserted
describe clock and reset operations. Per
t
C K IN L
4
3
t
C K IN
t
1
C K IN H
1
t
P F D
t
M S D
Figure 8. Clock and Reset Timing
22, combina-
t
W R S T
2
t
M S S
–24–
t
M S H
Min
25.0
10.0
10.0
11 t
2 t
2 t
CKIN
CKIN
CKIN
Max
100.0
15.0
15.0
REV. A
Unit
ns
ns
ns
ns
ns
ns
ns
ns

Related parts for ADSP-BF535PBBZ-200