ADSP-BF535PBBZ-200 Analog Devices Inc, ADSP-BF535PBBZ-200 Datasheet - Page 30

200/400MMAC 16-bit DSP MICROCOMPUTER

ADSP-BF535PBBZ-200

Manufacturer Part Number
ADSP-BF535PBBZ-200
Description
200/400MMAC 16-bit DSP MICROCOMPUTER
Manufacturer
Analog Devices Inc
Series
Blackfin®r
Type
Fixed Pointr

Specifications of ADSP-BF535PBBZ-200

Interface
PCI, SPI, SSP, UART, USB
Clock Rate
200MHz
Non-volatile Memory
External
On-chip Ram
308kB
Voltage - I/o
3.30V
Voltage - Core
1.50V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
260-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADSP-BF535PBBZ-200
Manufacturer:
Analog Devices Inc
Quantity:
10 000
ADSP-BF535
Serial Ports
Table 17
timing.
Table 17. Serial Ports—External Clock
1
Table 18. Serial Ports—Internal Clock
1
Table 19. Serial Ports—External or Internal Clock
1
Table 20. Serial Ports—External Clock
1
Table 21. Serial Ports—Internal Clock
1
Parameter
Timing Requirements
t
t
t
t
t
t
Parameter
Timing Requirements
t
t
t
t
Parameter
Switching Characteristics
t
t
Parameter
Switching Characteristics
t
t
t
t
Parameter
Switching Characteristics
t
t
t
t
t
Referenced to sample edge.
Referenced to sample edge.
Referenced to drive edge.
Referenced to drive edge.
Referenced to drive edge.
SFSE
HFSE
SDRE
HDRE
SCLKWE
SCLKE
SFSI
HFSI
SDRI
HDRI
DFSE
HOFSE
DFSE
HOFSE
DDTE
HDTE
DFSI
HOFSI
DDTI
HDTI
SCLKWI
through
Table 22
TFS/RFS Setup Before TCLK/RCLK
TFS/RFS Hold After TCLK/RCLK
Receive Data Setup Before RCLK
Receive Data Hold Before RCLK
TCLK/RCLK Width
TCLK/RCLK Period
TFS/RFS Setup Before TCLK/RCLK
TFS/RFS Hold After TCLK/RCLK
Receive Data Setup Before RCLK
Receive Data Hold Before RCLK
RFS Delay After RCLK (Internally Generated RFS)
RFS Hold After RCLK (Internally Generated RFS)
TFS Delay After TCLK (Internally Generated TFS)
TFS Hold After TCLK (Internally Generated TFS)
Transmit Data Delay After TCLK
Transmit Data Hold After TCLK
TFS Delay After TCLK (Internally Generated TFS)
TFS Hold After TCLK (Internally Generated TFS)
Transmit Data Delay After TCLK
Transmit Data Hold After TCLK
TCLK/RCLK Width
and
Figure 14
describe Serial Port
1
1
1
1
1
1
1
1
1
1
1
1
–30–
1
1
1
1
1
1
Min
3.0
3.0
3.0
3.0
(0.5 t
2 t
Min
7.0
2.0
7.0
4.0
Min
3.0
Min
3.0
3.0
Min
0.0
0.0
0.5 t
SCLK
SCLK
SCLKE
) – 1
Max
10.0
Max
10.0
10.0
Max
Max
6.0
8.0
Max
REV. A
Unit
ns
ns
Unit
ns
ns
ns
ns
Unit
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns

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