ADSP-BF535PBBZ-200 Analog Devices Inc, ADSP-BF535PBBZ-200 Datasheet - Page 35

• Manufacturer Part Number: ADSP-BF535PBBZ-200
• Description: 200/400MMAC 16-bit DSP MICROCOMPUTER
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF535PBBZ-200

• Interface: PCI, SPI, SSP, UART, USB
• Clock Rate: 200MHz
• Non-volatile Memory: External
• On-chip Ram: 308kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.50V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 260-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

JTAG Test and Emulation Port Timing
Table 25
Table 25. JTAG Port Timing
1
2
3
REV. A
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics
t
t
System Inputs=DATA31-0, ADDR25-2, ARDY, TMR2-0, PF15-0, RSCLK0, RFS0, DR0, TSCLK0, TFS0, RSCLK1, RFS1, DR1, TSCLK1, TFS1,
50 MHz max.
System Outputs=DATA31-0, ADDR25-2, ABE3-0/SDQM3-0, AOE, ARE, AWE, SCAS, CLKOUT/SCLK1, SCLK0, SCKE, SA10, SWE, SMS3-0,
TCK
STAP
HTAP
SSYS
HSYS
TRSTW
DTDO
DSYS
MOSI0, MISO0, SCK0, MOSI1, MISO1, SCK1, RX0, RX1, USB_CLK, XVER_DATA, DPLS, DMNS, NMI, RESET, BYPASS, BMODE2-0,
PCI_AD31-0, PCI_CBE3-0, PCI_FRAME, PCI_IRDY, PCI_TRDY, PCI_DEVSEL, PCI_STOP, PCI_PERR, PCI_PAR, PCI_SERR, PCI_RST,
PCI_GNT, PCI_IDSEL, PCI_LOCK, PCI_CLK, PCI_INTA, PCI_INTB, PCI_INTC, PCI_INTD.
SRAS, TMR2-0, PF15-0, RSCLK0, RFS0, TSCLK0, TFS0, DT0, RSCLK1, RFS1, TSCLK1, TFS1, DT1, MOSI0, MISO0, SCK0, MOSI1, MISO1,
SCK1, TX0, TX1, TXDPLS, TXDMNS, TXEN, SUSPEND, DEEPSLEEP, PCI_AD31-0, PCI_CBE3-0, PCI_FRAME, PCI_IRDY, PCI_TRDY,
PCI_DEVSEL, PCI_STOP, PCI_PERR, PCI_PAR, PCI_REQ, PCI_SERR, PCI_RST, PCI_INTA, EMU.
and
O U T P U TS
SY S T E M
S YS T E M
IN P U T S
Figure 18
T R ST
TCK Period
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK Low
System Inputs Hold After TCK Low
TRST Pulse Width
TDO Delay from TCK Low
System Outputs Delay After TCK Low
T M S
T D O
T C K
T D I
describe JTAG port operations.
2
t
D T D O
t
t
D S Y S
S T A P
Figure 18. JTAG Port Timing
t
T C K
1
1
3
t
H T A P
–35–
t
S S Y S
t
T R S T W
t
H S Y S
Min
20.0
4.0
0.0
ADSP-BF535
Max
4.0
4.0
4.0
5.0
7.0
15.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns