DSPIC33EP512MU810T-I/PT Microchip Technology, DSPIC33EP512MU810T-I/PT Datasheet - Page 127

• Manufacturer Part Number: DSPIC33EP512MU810T-I/PT
• Description: 100 PINS, 512KB Flash, 52KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 100 TQFP 12x12x1mm T
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33EPr

Specifications of DSPIC33EP512MU810T-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 60 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 83
• Program Memory Size: 512KB (170K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 24K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 5-1:
 2009-2011 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11-4
bit 3-0
Note 1:
R/SO-0
dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
WR
U-0
—
2:
3:
4:
5:
6:
(1)
These bits can only be reset on POR.
If this bit is set, upon exiting Idle mode there is a delay (T
operational.
All other combinations of NVMOP<3:0> are unimplemented.
The entire segment is erased with the exception of IVT.
Execution of the PWRSAV instruction is ignored while any of the NVM operations are in progress.
Two adjacent words are programmed during execution of this operation.
WR: Write Control bit
1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is
0 = Program or erase operation is complete and inactive
WREN: Write Enable bit
1 = Enable Flash program/erase operations
0 = Inhibit Flash program/erase operations
WRERR: Write Sequence Error Flag bit
1 = An improper program or erase sequence attempt or termination has occurred (bit is set
0 = The program or erase operation completed normally
NVMSIDL: NVM Stop-in-Idle Control bit
1 = Discontinue primary and auxiliary Flash operation when the device enters Idle mode
0 = Continue primary and auxiliary Flash operation when the device enters Idle mode
Unimplemented: Read as ‘0’
NVMOP<3:0>: NVM Operation Select bits
1111 = Reserved
1110 = Reserved
1101 = Bulk erase primary program Flash memory
1100 = Reserved
1011 = Reserved
1010 = Bulk erase auxiliary program Flash memory
0011 = Memory page erase operation
0010 = Memory row program operation
0001 = Memory word program operation
0000 = Program a single Configuration register byte
R/W-0
WREN
cleared by hardware once operation is complete
automatically on any set attempt of the WR bit)
U-0
NVMCON: NON-VOLATILE MEMORY (NVM) CONTROL REGISTER
—
(1)
SO = Settable only bit
W = Writable bit
‘1’ = Bit is set
R/W-0
WRERR
U-0
—
(1)
NVMSIDL
R/W-0
U-0
Preliminary
—
(2)
(2)
(6)
(3,5)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
U-0
—
(1)
VREG
) before Flash memory becomes
R/W-0
U-0
NVMOP<3:0>
—
(1)
x = Bit is unknown
R/W-0
(3,5)
U-0
—
(1)
DS70616E-page 127
R/W-0
U-0
—
(1)
bit 8
bit 0