DSPIC33EP512MU810T-I/PT Microchip Technology, DSPIC33EP512MU810T-I/PT Datasheet - Page 45

• Manufacturer Part Number: DSPIC33EP512MU810T-I/PT
• Description: 100 PINS, 512KB Flash, 52KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 100 TQFP 12x12x1mm T
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33EPr

Specifications of DSPIC33EP512MU810T-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 60 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 83
• Program Memory Size: 512KB (170K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 24K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.2
The
PIC24EPXXXGU810/814 CPU has a separate 16-bit
wide data memory space. The data space is accessed
using separate Address Generation Units (AGUs) for
read and write operations. The data memory maps are
shown in
Figure
All Effective Addresses (EAs) in the data memory space
are 16 bits wide and point to bytes within the data space.
This arrangement gives a base data space address
range of 64 Kbytes or 32K words.
The base data space address is used in conjunction with
a read or write page register (DSRPAG or DSWPAG) to
form an extended data space, which has a total address
range of 16 MBytes.
dsPIC33EPXXXMU806/810/814
PIC24EPXXXGU810/814 devices implement up to
56 Kbytes of data memory. If an EA point to a location
outside of this area, an all-zero word or byte is returned.
4.2.1
The data memory space is organized in byte
addressable, 16-bit wide blocks. Data is aligned in data
memory and registers as 16-bit words, but all data
space EAs resolve to bytes. The Least Significant
Bytes (LSBs) of each word have even addresses, while
the Most Significant Bytes (MSBs) have odd
addresses.
4.2.2
To maintain backward compatibility with PIC
devices and improve data space memory usage
efficiency, the dsPIC33EPXXXMU806/810/814 and
PIC24EPXXXGU810/814 instruction set supports both
word and byte operations. As a consequence of byte
accessibility, all effective address calculations are
internally scaled to step through word-aligned memory.
For example, the core recognizes that Post-Modified
Register Indirect Addressing mode [Ws++] results in a
value of Ws + 1 for byte operations and Ws + 2 for word
operations.
A data byte read, reads the complete word that
contains the byte, using the LSB of any EA to
determine which byte to select. The selected byte is
placed onto the LSB of the data path. That is, data
memory and registers are organized as two parallel
byte-wide entities with shared (word) address decode
but separate write lines. Data byte writes only write to
the corresponding side of the array or register that
matches the byte address.
 2009-2011 Microchip Technology Inc.
dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
4-6.
Data Address Space
dsPIC33EPXXXMU806/810/814
DATA SPACE WIDTH
DATA MEMORY ORGANIZATION
AND ALIGNMENT
Figure
4-3,
Figure
4-4,
Figure 4-5
®
MCU
and
and
and
Preliminary
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word
operations, or translating from 8-bit MCU code. If a
misaligned read or write is attempted, an address error
trap is generated. If the error occurred on a read, the
instruction underway is completed. If the error occurred
on a write, the instruction is executed but the write does
not occur. In either case, a trap is then executed,
allowing the system and/or user application to examine
the machine state prior to execution of the address
Fault.
All byte loads into any W register are loaded into the
LSB. The MSB is not modified.
A Sign-Extend instruction (SE) is provided to allow user
applications to translate 8-bit signed data to 16-bit
signed values. Alternatively, for 16-bit unsigned data,
user applications can clear the MSB of any W register
by executing a Zero-Extend (ZE) instruction on the
appropriate address.
4.2.3
The first 4 Kbytes of the Near Data Space, from 0x0000
to 0x0FFF, is primarily occupied by Special Function
Registers
dsPIC33EPXXXMU806/810/814
PIC24EPXXXGU810/814 core and peripheral modules
for controlling the operation of the device.
SFRs are distributed among the modules that they
control, and are generally grouped together by module.
Much of the SFR space contains unused addresses;
these are read as ‘0’.
4.2.4
The 8 Kbyte area between 0x0000 and 0x1FFF is
referred to as the near data space. Locations in this
space are directly addressable through a 13-bit abso-
lute address field within all memory direct instructions.
Additionally, the whole data space is addressable using
MOV instructions, which support Memory Direct
Addressing mode with a 16-bit address field, or by
using Indirect Addressing mode using a working
register as an Address Pointer.
Note:
SFR SPACE
The actual set of peripheral features and
interrupts varies by the device. Refer to
the corresponding device tables and
pinout
information.
NEAR DATA SPACE
(SFRs).
diagrams
These
are
for
DS70616E-page 45
used
device-specific
by
and
the