DSPIC33EP512MU810T-I/PT Microchip Technology, DSPIC33EP512MU810T-I/PT Datasheet - Page 473

• Manufacturer Part Number: DSPIC33EP512MU810T-I/PT
• Description: 100 PINS, 512KB Flash, 52KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 100 TQFP 12x12x1mm T
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33EPr

Specifications of DSPIC33EP512MU810T-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 60 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 83
• Program Memory Size: 512KB (170K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 24K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 32-17: PLL CLOCK TIMING SPECIFICATIONS
TABLE 32-18: AUXILIARY PLL CLOCK TIMING SPECIFICATIONS
 2009-2011 Microchip Technology Inc.
AC CHARACTERISTICS
OS50
OS51
OS52
OS53
Note 1:
AC CHARACTERISTICS
OS54
OS55
OS56
OS57
Note 1:
Param. Symbol
Param. Symbol
dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
2:
F
F
T
D
F
F
T
D
PLLI
SYS
LOCK
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
This jitter specification is based on clock cycle-by-clock cycle measurements. To get the effective jitter for
individual time bases or communication clocks used by the application, use the following formula:
For example, if F
PLLI
SYS
LOCK
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
CLK
CLK
PLL Voltage Controlled
Oscillator (VCO) Input
Frequency Range
On-Chip VCO System
Frequency
PLL Start-up Time (Lock Time)
CLKO Stability (Jitter)
PLL Voltage Controlled
Oscillator (VCO) Input
Frequency Range
On-Chip VCO System
Frequency
PLL Start-up Time (Lock Time)
CLKO Stability (Jitter)
OSC
Characteristic
Characteristic
= 120 MHz and the SPI bit rate = 10 MHz, the effective jitter is as follows:
Effective Jitter
(2)
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature
Effective Jitter
Preliminary
=
-------------------------------------------------------------------------------------------
Min.
Min.
120
0.8
0.9
0.9
60
-5
-2
-------------------------------------------------------------------------------------- -
Time Base or Communication Clock
3
=
D
------------- -
CLK
120
-------- -
10
Typ.
Typ.
0.25
1.5
0.5
1.5
—
—
—
—
=
-40°C  T
-40°C  T
-40°C  T
-40°C  T
(1)
(1)
D
D
------------- -
F
CLK
CLK
12
OSC
Max.
Max.
340
120
8.0
3.1
5.5
3.1
5
2
=
A
A
A
A
D
------------- -
3.464
 +85°C for Industrial
 +125°C for Extended
 +85°C for Industrial
 +125°C for Extended
CLK
Units
Units
MHz ECPLL, XTPLL modes
MHz
MHz ECPLL, XTPLL modes
MHz
mS
mS
%
%
Conditions
Conditions
DS70616E-page 473
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