DSPIC33EP512MU810T-I/PT Microchip Technology, DSPIC33EP512MU810T-I/PT Datasheet - Page 297

• Manufacturer Part Number: DSPIC33EP512MU810T-I/PT
• Description: 100 PINS, 512KB Flash, 52KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 100 TQFP 12x12x1mm T
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33EPr

Specifications of DSPIC33EP512MU810T-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 60 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 83
• Program Memory Size: 512KB (170K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 24K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 17-1:
 2009-2011 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12-10
bit 9-8
bit 7
bit 6-4
Note 1:
QEIEN
R/W-0
dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
U-0
—
2:
3:
When CCM = 10 or CCM = 11, all of the QEI counters operate as timers and the PIMOD<2:0> bits are
ignored.
When CCM = 00 and QEA and QEB values match Index Match Value (IMV), the POSCNTH and
POSCNTL registers are reset.
The selected clock rate should be at least twice the expected maximum quadrature count rate.
QEIEN: Quadrature Encoder Interface Module Counter Enable bit
1 = Module counters are enabled
0 = Module counters are disabled, but SFRs can be read or written to
Unimplemented: Read as ‘0’
QEISIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
PIMOD<2:0>: Position Counter Initialization Mode Select bits
111 = Reserved
110 = Modulo count mode for position counter
101 = Resets the position counter when the position counter equals QEIxGEC register
100 = Second index event after home event initializes position counter with contents of QEIxIC
011 = First index event after home event initializes position counter with contents of QEIxIC register
010 = Next index input event initializes the position counter with contents of QEIxIC register
001 = Every Index input event resets the position counter
000 = Index input event does not affect position counter
IMV<1:0>: Index Match Value bits
11 = Index match occurs when QEB = 1 and QEA = 1
10 = Index match occurs when QEB = 1 and QEA = 0
01 = Index match occurs when QEB = 0 and QEA = 1
00 = Index input event does not affect position counter
Unimplemented: Read as ‘0’
INTDIV<2:0>: Timer Input Clock Prescale Select bits (interval timer, main timer (position counter),
velocity counter and index counter internal clock divider select)
111 = 1:256 prescale value
110 = 1:64 prescale value
101 = 1:32 prescale value
100 = 1:16 prescale value
011 = 1:8 prescale value
010 = 1:4 prescale value
001 = 1:2 prescale value
000 = 1:1 prescale value
R/W-0
U-0
—
QEIxCON: QEI CONTROL REGISTER
register
INTDIV<2:0>
W = Writable bit
‘1’ = Bit is set
QEISIDL
R/W-0
R/W-0
(3)
R/W-0
R/W-0
(2)
Preliminary
PIMOD<2:0>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
CNTPOL
R/W-0
R/W-0
(1)
GATEN
R/W-0
R/W-0
(1)
(3)
x = Bit is unknown
R/W-0
R/W-0
IMV<1:0>
CCM<1:0>
DS70616E-page 297
(2)
R/W-0
R/W-0
bit 8
bit 0