DSPIC33EP512MU810T-I/PT Microchip Technology, DSPIC33EP512MU810T-I/PT Datasheet - Page 551

• Manufacturer Part Number: DSPIC33EP512MU810T-I/PT
• Description: 100 PINS, 512KB Flash, 52KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 100 TQFP 12x12x1mm T
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33EPr

Specifications of DSPIC33EP512MU810T-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 60 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 83
• Program Memory Size: 512KB (170K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 24K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

APPENDIX A:
Revision A (December 2009)
This is the initial released version of this document.
Revision B (July 2010)
This revision includes minor typographical and
formatting changes throughout the data sheet text.
The major changes are referenced by their respective
section in
TABLE A-1:
 2009-2011 Microchip Technology Inc.
“High-Performance, 16-bit Digital
Signal Controllers and
Microcontrollers”
Section 1.0 “Device Overview”
Section 2.0 “Guidelines for
Getting Started with 16-bit Digital
Signal Controllers and
Microcontrollers”
Section 3.0 “CPU”
dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
Table
Section Name
A-1.
MAJOR SECTION UPDATES
REVISION HISTORY
Removed reference to dual triggers for Motor Control Peripherals.
Relocated the V
and Table 3).
Added SCK2, SDI2, SDO2 pins in pin location 4,5 and 6 respectively in 64-pin
QFN.
Added SCK2, SDI2, SDO2 pins in pin location 4,5 and 6 respectively in 64-pin
TQFP.
Added SCK2, SDI2, SDO2 pins in pin location 10,11 and 12 respectively in
100-pin TQFP.
Added SCK2, SDI2, SDO2 pins in Table 2 and Table 3.
Moved the RP30 pin to pin location 95, and the RP31 pin to pin location 96 in
the 144-pin TQFP and 144-pin LQFP pin diagrams.
Removed the SCL1 and SDA1 pins from the Pinout I/O Descriptions (see
Table 1-1).
Removed Section 2.8 “Configuration of Analog and Digital Pins During ICSP
Operations”
Added Note 4 to the CPU Status Register (SR) in Register 3-1.
Added the VAR bit (CORCON<15>) to Register 3-2.
Preliminary
BUSST
pin in all pin diagrams (see “Pin Diagrams”, Table 2
Update Description
DS70616E-page 551