DSPIC33EP512MU810T-I/PT Microchip Technology, DSPIC33EP512MU810T-I/PT Datasheet - Page 191

• Manufacturer Part Number: DSPIC33EP512MU810T-I/PT
• Description: 100 PINS, 512KB Flash, 52KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 100 TQFP 12x12x1mm T
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33EPr

Specifications of DSPIC33EP512MU810T-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 60 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 83
• Program Memory Size: 512KB (170K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 24K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

11.4
A major challenge in general purpose devices is provid-
ing the largest possible set of peripheral features while
minimizing the conflict of features on I/O pins. The chal-
lenge is even greater on low pin-count devices. In an
application where more than one peripheral needs to
be assigned to a single pin, inconvenient workarounds
in application code or a complete redesign may be the
only option.
Peripheral pin select configuration provides an
alternative to these choices by enabling peripheral set
selection and their placement on a wide range of I/O
pins. By increasing the pinout options available on a
particular device, users can better tailor the device to
their entire application, rather than trimming the
application to fit the device.
The peripheral pin select configuration feature oper-
ates over a fixed subset of digital I/O pins. Users may
independently map the input and/or output of most dig-
ital peripherals to any one of these I/O pins. Peripheral
pin select is performed in software and generally does
not require the device to be reprogrammed. Hardware
safeguards are included that prevent accidental or
spurious changes to the peripheral mapping once it has
been established.
11.4.1
The number of available pins is dependent on the
particular device and its pin count. Pins that support the
peripheral pin select feature include the designation
“RPn” or “RPIn” in their full pin designation, where “RP”
designates a remappable function for input or output
and “RPI” designates a remappable functions for input
only, and “n” is the remappable pin number.
11.4.2
The peripherals managed by the peripheral pin select
are all digital-only peripherals. These include general
serial communications (UART and SPI), general pur-
pose timer clock inputs, timer-related peripherals (input
capture and output compare) and interrupt-on-change
inputs.
In comparison, some digital-only peripheral modules
are never included in the peripheral pin select feature.
This is because the peripheral’s function requires spe-
cial I/O circuitry on a specific port and cannot be easily
connected to multiple pins. These modules include I
and the PWM. A similar requirement excludes all mod-
ules with analog inputs, such as the A/D converter.
A key difference between remappable and non-remap-
pable peripherals is that remappable peripherals are
not associated with a default I/O pin. The peripheral
must always be assigned to a specific I/O pin before it
can be used. In contrast, non-remappable peripherals
are always available on a default pin, assuming that the
peripheral is active and not conflicting with another
peripheral.
 2009-2011 Microchip Technology Inc.
dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
Peripheral Pin Select
AVAILABLE PINS
AVAILABLE PERIPHERALS
Preliminary
2
C
When a remappable peripheral is active on a given I/O
pin, it takes priority over all other digital I/O and digital
communication peripherals associated with the pin.
Priority is given regardless of the type of peripheral that
is mapped. Remappable peripherals never take priority
over any analog functions associated with the pin.
11.4.3
Peripheral pin select features are controlled through
two sets of SFRs: one to map peripheral inputs, and
one to map outputs. Because they are separately con-
trolled, a particular peripheral’s input and output (if the
peripheral has both) can be placed on any selectable
function pin without constraint.
The association of a peripheral to a peripheral-select-
able pin is handled in two different ways, depending on
whether an input or output is being mapped.
11.4.3.1
The inputs of the peripheral pin select options are
mapped on the basis of the peripheral. That is, a control
register associated with a peripheral dictates the pin it
will be mapped to. The RPINRx registers are used to
configure peripheral input mapping (see
through
7-bit fields, with each set associated with one of the
remappable peripherals (see
a given peripheral’s bit field with an appropriate 7-bit
value maps the RPn/RPIn pin with the corresponding
value to that peripheral (see
device, the valid range of values for any bit field corre-
sponds to the maximum number of peripheral pin selec-
tions supported by the device.
For example,
selection for the U1RX input.
FIGURE 11-2:
RPn/RPIn
Note:
RP0
RP1
RP3
Register
For input only, peripheral pin select functionality
does not have priority over TRISx settings.
Therefore, when configuring RPn/RPIn pin for
input, the corresponding bit in the TRISx register
must also be configured for input (set to ‘1’).
CONTROLLING PERIPHERAL PIN
SELECT
INPUT MAPPING
Figure 11-2
11-22). Each register contains sets of
U1RX REMAPPABLE INPUT
illustrates remappable pin
Table
Table
U1RXR<6:0>
n
0
1
2
11-2). For any given
11-1). Programming
DS70616E-page 191
U1RX input
to peripheral
Register 11-1