DSPIC33EP512MU810T-I/PT Microchip Technology, DSPIC33EP512MU810T-I/PT Datasheet - Page 344

• Manufacturer Part Number: DSPIC33EP512MU810T-I/PT
• Description: 100 PINS, 512KB Flash, 52KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 100 TQFP 12x12x1mm T
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33EPr

Specifications of DSPIC33EP512MU810T-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 60 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 83
• Program Memory Size: 512KB (170K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 24K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
REGISTER 21-17: CiRXFnEID: ECAN™ ACCEPTANCE FILTER EXTENDED IDENTIFIER REGISTER
REGISTER 21-18: CiFMSKSEL1: ECAN™ FILTER 7-0 MASK SELECTION REGISTER
DS70616E-page 344
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-0
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-14
bit 13-12
bit 11-10
bit 9-8
bit 7-6
bit 5-4
bit 3-2
bit 1-0
R/W-0
R/W-0
R/W-x
EID15
R/W-x
EID7
F7MSK<1:0>
F3MSK<1:0>
EID<15:0>: Extended Identifier bits
1 = Message address bit EIDx must be ‘1’ to match filter
0 = Message address bit EIDx must be ‘0’ to match filter
F7MSK<1:0>: Mask Source for Filter 7 bit
11 = Reserved
10 = Acceptance Mask 2 registers contain mask
01 = Acceptance Mask 1 registers contain mask
00 = Acceptance Mask 0 registers contain mask
F6MSK<1:0>: Mask Source for Filter 6 bit (same values as bit 15-14)
F5MSK<1:0>: Mask Source for Filter 5 bit (same values as bit 15-14)
F4MSK<1:0>: Mask Source for Filter 4 bit (same values as bit 15-14)
F3MSK<1:0>: Mask Source for Filter 3 bit (same values as bit 15-14)
F2MSK<1:0>: Mask Source for Filter 2 bit (same values as bit 15-14)
F1MSK<1:0>: Mask Source for Filter 1 bit (same values as bit 15-14)
F0MSK<1:0>: Mask Source for Filter 0 bit (same values as bit 15-14)
R/W-x
EID14
R/W-x
R/W-0
R/W-0
EID6
n (n = 0-15)
C = Writable bit, but only ‘0’ can be written to clear the bit
W = Writable bit
‘1’ = Bit is set
C = Writable bit, but only ‘0’ can be written to clear the bit
W = Writable bit
‘1’ = Bit is set
R/W-x
EID13
R/W-x
R/W-0
R/W-0
EID5
F6MSK<1:0>
F2MSK<1:0>
R/W-x
EID12
R/W-x
R/W-0
R/W-0
EID4
Preliminary
U = Unimplemented bit, read as ‘0’
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
‘0’ = Bit is cleared
R/W-x
R/W-x
R/W-0
R/W-0
EID11
EID3
F5MSK<1:0>
F1MSK<1:0>
R/W-x
EID10
R/W-x
R/W-0
R/W-0
EID2
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x = Bit is unknown
x = Bit is unknown
R/W-0
R/W-0
R/W-x
R/W-x
EID9
EID1
F4MSK<1:0>
F0MSK<1:0>
R/W-x
R/W-x
R/W-0
R/W-0
EID8
EID0
bit 8
bit 0
bit 8
bit 0