EVAL-ADUC7060QSPZ Analog Devices Inc, EVAL-ADUC7060QSPZ Datasheet - Page 11

• Manufacturer Part Number: EVAL-ADUC7060QSPZ
• Description: Quick Start Development System
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ PLUS Kitr
• Type: MCU, ARM7r

Specifications of EVAL-ADUC7060QSPZ

• Contents: Evaluation Board, Power Supply, Cable, Software, Emulator and Documentation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC7060
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q5189809

Table 5. SPI Slave Mode Timing (Phase Mode = 1)
Parameter
t
t
t
t
t
t
t
t
t
t
t
1
2
CS
SL
SH
DAV
DSU
DHD
DF
DR
SR
SF
SFS
t
t
UCLK
HCLK
=97.6 ns. It corresponds to the 10.24 MHz internal clock from the PLL before the clock divider.
depends on the clock divider or CD bits in PLLCON MMR. t
(POLARITY = 0)
(POLARITY = 1)
(POLARITY = 0)
(POLARITY = 1)
Description
CS to SCLOCK edge
SCLOCK low pulse width
SCLOCK high pulse width
Data output valid after SCLOCK edge
Data input setup time before SCLOCK edge
Data input hold time after SCLOCK edge
Data output fall time
Data output rise time
SCLOCK rise time
SCLOCK fall time
CS high after SCLOCK edge
SCLOCK
SCLOCK
SCLOCK
SCLOCK
MOSI
MISO
MISO
MOSI
CS
1
t
t
CS
DOSU
t
DSU
MSB IN
2
2
t
t
DSU
DAV
MSB
t
DHD
t
t
SH
SH
Figure 4. SPI Master Mode Timing (Phase Mode = 0)
Figure 5. SPI Slave Mode Timing (Phase Mode = 1)
t
DF
HCLK
MSB IN
t
DAV
= t
1
t
DHD
UCLK
t
t
1
MSB
SL
SL
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CD
t
DR
t
.
BITS 6 TO 1
BITS 6 TO 1
DF
Min
(2 × t
1 × t
2 × t
1
1
0
t
UCLK
UCLK
DR
BITS 6 TO 1
HCLK
BITS 6 TO 1
) + (2 × t
UCLK
LSB IN
t
t
SR
SR
)
LSB
Typ
(SPIDIV + 1) × t
(SPIDIV + 1) × t
30
30
LSB IN
t
t
SF
SF
LSB
t
SFS
HCLK
HCLK
ADuC7060
Max
40
40
40
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns