EVAL-ADUC7060QSPZ Analog Devices Inc, EVAL-ADUC7060QSPZ Datasheet - Page 38

• Manufacturer Part Number: EVAL-ADUC7060QSPZ
• Description: Quick Start Development System
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ PLUS Kitr
• Type: MCU, ARM7r

Specifications of EVAL-ADUC7060QSPZ

• Contents: Evaluation Board, Power Supply, Cable, Software, Emulator and Documentation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC7060
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q5189809

ADuC7060
ADC Interrupt Mask Register
Name:
Address:
Default value:
Access:
Function:
Table 39. ADCMSKI MMR Bit Designations
Bit
7
6
5
4
3
2
1
0
ADC Mode Register
Name:
Address:
Default value:
Access:
Function:
Table 40. ADCMDE MMR Bit Designations
Bit
7
6
5
Name
ADC0ATHEX_INTEN
ADC0THEX_INTEN
ADC0OVR_INTEN
ADC1RDY_INTEN
ADC0RDY_INTEN
Name
ADCCLKSEL
ADCLPMEN
ADCMSKI
0xFFFF0504
0x0000
Read and write
This register allows the ADC interrupt sources to be enabled individually. The bit positions in this register are the same
as the lower eight bits in the ADCSTA MMR. If a bit is set by user code to 1, the respective interrupt is enabled. By
default, all bits are 0, meaning all ADC interrupt sources are disabled.
ADCMDE
0xFFFF0508
0x03
Read and write
The ADC mode MMR is an 8-bit register that configures the mode of operation of the ADC subsystem.
When set to 1, this bit enables an interrupt when the ADC0OVR bit in the ADCSTA register is set.
Description
Not used. These bits are reserved for future functionality and should not be monitored by user code.
ADC0 accumulator comparator threshold exceeded interrupt enable bit.
When set to 1, this bit enables an interrupt when the ADC0ATHEX bit in the ADCSTA register is set.
When this bit is cleared, this interrupt source is disabled.
Not used. These bits are reserved for future functionality and should not be monitored by user code.
Primary channel ADC comparator threshold exceeded interrupt enable bit.
When set to 1, this bit enables an interrupt when the ADC0THEX bit in the ADCSTA register is set.
When this bit is cleared, this interrupt source is disabled.
When this bit is cleared, this interrupt source is disabled.
Not used. These bits are reserved for future functionality and should not be monitored by user code.
Auxiliary ADC result ready bit.
When set to 1, this bit enables an interrupt when the ADC1RDY bit in the ADCSTA register is set.
When this bit is cleared, this interrupt source is disabled.
Primary ADC result ready bit.
When set to 1, this bit enables an interrupt when the ADC0RDY bit in the ADCSTA register is set.
When this bit is cleared, this interrupt source is disabled.
Description
Set this bit to 1 to enable ADCCLK = 4 MHz. This bit should be set for normal ADC operation.
Clear this bit to enable ADCCLK = 131 kHz. This bit should be cleared for low power ADC operation.
Not used. These bits are reserved for future functionality and should not be monitored by user code.
Enable low power mode. This bit has no effect if ADCMDE[4:3] = 00.
This bit must be set to 1 in low power mode.
Clearing this bit in low power mode results in erratic ADC results.
This bit has no effect if the ADC is in normal mode.
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