EVAL-ADUC7060QSPZ Analog Devices Inc, EVAL-ADUC7060QSPZ Datasheet - Page 82

• Manufacturer Part Number: EVAL-ADUC7060QSPZ
• Description: Quick Start Development System
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ PLUS Kitr
• Type: MCU, ARM7r

Specifications of EVAL-ADUC7060QSPZ

• Contents: Evaluation Board, Power Supply, Cable, Software, Emulator and Documentation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC7060
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q5189809

ADuC7060
SERIAL CLOCK GENERATION
The I
transfer. The master channel can be configured to operate in
fast mode (400 kHz) or standard mode (100 kHz).
The bit rate is defined in the I2CDIV MMR as follows:
where:
f
DIVH is the the high period of the clock.
DIVL is the the low period of the clock.
Thus, for 100 kHz operation
and for 400 kHz
The I2CDIV register corresponds to DIVH:DIVL.
I
Slave Mode
In slave mode, the I2CID0, I2CID1, I2CID2, and I2CID3
registers contain the device IDs. The device compares the four
I2CIDx registers to the address byte received from the bus
master. To be correctly addressed, the 7 MSBs of either ID
register must be identical to that of the 7 MSBs of the first
received address byte. The least significant bit of the ID registers
(the transfer direction bit) is ignored in the process of address
recognition.
The ADuC7060 also supports 10-bit addressing mode. When
Bit 1 of I2CSCON (ADR10EN bit) is set to 1, then one 10-bit
address is supported in slave mode and is stored in the I2CID0
and I2CID1 registers. The 10-bit address is derived as follows:
I2CID0[0] is the read/write bit and is not part of the I
address.
UCLK
2
C BUS ADDRESSES
DIVH = DIVL = 0x33
DIVH = 0x0A, DIVL = 0x0F
is the clock before the clock divider.
2
f
C master in the system generates the serial clock for a
SERIAL
CLOCK
=
2 (
+
DIVH
f
UCLK
)
+
(2
+
DIVL
)
2
C
Rev. 0 | Page 82 of 100
I2CID0[7:1] = Address Bits[6:0].
I2CID1[2:0] = Address Bits[9:7].
I2CID1[7:3] must be set to 11110b
Master Mode
In master mode, the I2CADR0 register is programmed with the
I
In 7-bit address mode, I2CADR0[7:1] are set to the device
address. I2CADR0[0] is the read/write bit.
In 10-bit address mode, the 10-bit address is created as follows:
I2CADR0[7:3] must be set to 11110b.
I2CADR0[2:1] = Address Bits[9:8].
I2CADR1[7:0] = Address Bits[7:0].
I2CADR0[0] is the read/write bit.
I
The I
of these are master related only, seven are slave related only, and
two MMRs are common to both master and slave modes.
I
I
Name:
Address:
Default
value:
Access:
Function:
2
2
2
2
C address of the device.
C Master Registers
C REGISTERS
C Master Control, I2CMCON Register
2
C peripheral interface consists overall of 19 MMRs. Ten
I2CMCON
0xFFFF0900
0x0000
Read and write
This 16-bit MMR configures the I
master mode.
2
C peripheral in