EVAL-ADUC7060QSPZ Analog Devices Inc, EVAL-ADUC7060QSPZ Datasheet - Page 47

• Manufacturer Part Number: EVAL-ADUC7060QSPZ
• Description: Quick Start Development System
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ PLUS Kitr
• Type: MCU, ARM7r

Specifications of EVAL-ADUC7060QSPZ

• Contents: Evaluation Board, Power Supply, Cable, Software, Emulator and Documentation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC7060
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q5189809

Primary Channel ADC Threshold Register
Name:
Address:
Default value:
Access:
Function:
Table 55. ADC0TH MMR Bit Designations
Bits
15 to 0
Primary Channel ADC Threshold Count Limit Register
Name:
Address:
Default value:
Access:
Function:
ADC0TH
0xFFFF053C
0x0000
Read and write
This 16-bit MMR sets the threshold against
which the absolute value of the primary ADC
conversion result is compared. In unipolar
mode, ADC0TH[15:0] are compared, and in
twos complement mode, ADC0TH[14:0] are
compared.
Description
ADC0 16-bit comparator threshold register.
ADC0THC
0xFFFF0540
0x0001
Read and write
This 8-bit MMR determines how many
cumulative (values below the threshold
decrement or reset the count to 0) primary
ADC conversion result readings above
ADC0TH must occur before the primary
ADC comparator threshold bit is set in the
ADCSTA MMR generating an ADC
interrupt. The primary ADC comparator
threshold bit is asserted as soon as the
ADC0THV = ADC0RCR.
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Table 56. ADC0THC MMR Bit Designations
Bits
7 to 0
Primary Channel ADC Threshold Count Register
Name:
Address:
Default value:
Access:
Function:
Table 57. ADC0THV MMR Bit Designations
Bits
7 to 0
Primary Channel ADC Accumulator Register
Name:
Address:
Default value:
Access:
Function:
Description
ADC0 8-bit threshold exceeded counter register.
Description
ADC0 8-bit threshold counter limit register.
ADC0ACC
0xFFFF0548
0x00000000
Read only
This 32-bit MMR holds the primary ADC
accumulator value. The primary ADC ready bit
in the ADCSTA MMR should be used to
determine when it is safe to read this MMR.
The MMR value is reset to 0 by disabling the
accumulator in the ADCCFG MMR or
reconfiguring the primary channel ADC.
ADC0THV
0xFFFF0544
0x0000
Read only
This 8-bit MMR is incremented every time
the absolute value of a primary ADC
conversion result |Result| ≥ ADC0TH. This
register is decremented or reset to 0 every
time the absolute value of a primary ADC
conversion result |Result| < ADC0TH. The
configuration of this function is enabled via
the primary channel ADC comparator bits in
the ADCCFG MMR.
ADuC7060