EVAL-ADUC7060QSPZ Analog Devices Inc, EVAL-ADUC7060QSPZ Datasheet - Page 70

• Manufacturer Part Number: EVAL-ADUC7060QSPZ
• Description: Quick Start Development System
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ PLUS Kitr
• Type: MCU, ARM7r

Specifications of EVAL-ADUC7060QSPZ

• Contents: Evaluation Board, Power Supply, Cable, Software, Emulator and Documentation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC7060
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q5189809

ADuC7060
PULSE-WIDTH MODULATOR
PULSE-WIDTH MODULATOR GENERAL OVERVIEW
The ADuC7060 integrates a 6-channel pulse-width modulator
(PWM) interface. The PWM outputs can be configured to drive
an H-bridge or can be used as standard PWM outputs. On
power-up, the PWM outputs default to H-bridge mode. This
ensures that the motor is turned off by default. In standard
PWM mode, the outputs are arranged as three pairs of PWM
pins. Users have control over the period of each pair of outputs
and over the duty cycle of each individual output.
Table 81. PWM MMRs
MMR Name
PWMCON
PWM0COM0
PWM0COM1
PWM0COM2
PWM0LEN
PWM1COM0
PWM1COM1
PWM1COM2
PWM1LEN
PWM2COM0
PWM2COM1
PWM2COM2
PWM2LEN
PWMICLR
Description
PWM control.
Compare Register 0 for PWM Output 0 and
Output 1.
Compare Register 1 for PWM Output 0 and
PWM Output 1.
Compare Register 2 for PWM Output 0 and
PWM Output 1.
Frequency control for PWM Output 0 and PWM
Output 1.
Compare Register 0 for PWM Output 2 and
PWM Output 3.
Compare Register 1 for PWM Output 2 and
PWM Output 3.
Compare Register 2 for PWM Output 2 and
PWM Output 3.
Frequency control for PWM Output 2 and PWM
Output 3.
Compare Register 0 for PWM Output 4 and
PWM Output 5.
Compare Register 1 for PWM Output 4 and
PWM Output 5.
Compare Register 2 for PWM Output 4 and
PWM Output 5.
Frequency control for PWM Output 4 and PWM
Output 5.
PWM interrupt clear.
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In all modes, the PWMxCOMx MMRs control the point at
which the PWM outputs change state. An example of the first
pair of PWM outputs (PWM0 and PWM1) is shown in Figure 25.
The PWM clock is selectable via PWMCON with one of the
following values: UCLK divided by 2, 4, 8, 16, 32, 64, 128, or
256. The length of a PWM period is defined by PWMxLEN.
The PWM waveforms are set by the count value of the 16-bit
timer and the compare registers contents as shown with the
PWM0 and PWM1 waveforms in Figure 25.
The low-side waveform, PWM1, goes high when the timer
count reaches PWM0LEN, and it goes low when the timer
count reaches the value held in PWM0COM2 or when the
high-side waveform (PWM0) goes low.
The high-side waveform, PWM0, goes high when the timer
count reaches the value held in PWM0COM0, and it goes low
when the timer count reaches the value held in PWM0COM1.
HIGH SIDE
LOW SIDE
(PWM0)
(PWM1)
PWM0COM2
PWM0COM1
PWM0COM0
PWMLEN0
Figure 25. PWM Timing