EVAL-ADUC7060QSPZ Analog Devices Inc, EVAL-ADUC7060QSPZ Datasheet - Page 57

• Manufacturer Part Number: EVAL-ADUC7060QSPZ
• Description: Quick Start Development System
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ PLUS Kitr
• Type: MCU, ARM7r

Specifications of EVAL-ADUC7060QSPZ

• Contents: Evaluation Board, Power Supply, Cable, Software, Emulator and Documentation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC7060
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q5189809

Table 66. IRQVEC MMR Bit Designations
Bit
31:23
22:7
6:2
1:0
Priority Registers
The IRQ interrupt vector register, IRQVEC, points to a memory
address containing a pointer to the interrupt service routine of
the currently active IRQ. This register should be read only when
an IRQ occurs and IRQ interrupt nesting has been enabled by
setting Bit 0 of the IRQCONN register.
IRQP0 Register
Name:
Address:
Default value:
Access:
Table 67. IRQP0 MMR Bit Designations
Bit
31:27
26:24
23
22:20
19
18:16
15
14:12
11:7
6:4
3:0
Type
Read
only
Read
only
Read
only
Reserved
Name
Reserved
T3PI
Reserved
T2PI
Reserved
T1PI
Reserved
T0PI
Reserved
SWINTP
Reserved
IRQP0
0xFFFF0020
0x00000000
Read and write
A priority level of 0 to 7 can be set for
A priority level of 0 to 7 can be set for
A priority level of 0 to 7 can be set for
A priority level of 0 to 7 can be set for
A priority level of 0 to 7 can be set for the
Initial
Value
0
0
0
0
Description
Reserved bits.
Timer3.
Reserved bit.
Timer2.
Reserved bit.
Timer1.
Reserved bit.
Timer0.
Reserved bits.
software interrupt source.
Interrupt 0 cannot be prioritized.
Description
Always read as 0.
IRQBASE register value.
Highest priority IRQ source. This
is a value between 0 to 19 repre-
senting the possible interrupt
sources. For example, if the highest
currently active IRQ is Timer1, then
these bits are [01000].
Reserved bits.
Rev. 0 | Page 57 of 100
IRQP1 Register
Name:
Address:
Default value:
Access:
Table 68. IRQP1 MMR Bit Designations
Bit
31
30:28
27
26:24
23
22:20
19
18:16
15
14:12
11
10:8
7:0
IRQP2 Register
Name:
Address:
Default value:
Access:
Table 69. IRQP2 MMR Bit Designations
Bit
31:15
14:12
11
10:8
7
6:4
3
2:0
Name
Reserved
I2CMPI
Reserved
IRQ1PI
Reserved
IRQ0PI
Reserved
SPIMPI
Reserved
UARTPI
Reserved
ADCPI
Reserved
Name
Reserved
IRQ3PI
Reserved
IRQ2PI
Reserved
SPISPI
Reserved
I2CSPI
IRQP1
0xFFFF0024
0x00000000
Read and write
IRQP2
0xFFFF0028
0x00000000
Read and write
Description
Reserved bit.
A priority level of 0 to 7 can be set for I
master.
Reserved bit.
A priority level of 0 to 7 can be set for IRQ1.
Reserved bit.
A priority level of 0 to 7 can be set for IRQ0.
Reserved bit.
A priority level of 0 to 7 can be set for SPI
master.
Reserved bit.
A priority level of 0 to 7 can be set for UART.
Reserved bit.
A priority level of 0 to 7 can be set for the
ADC interrupt source.
Reserved bits.
Description
Reserved bit.
A priority level of 0 to 7 can be set for IRQ3.
Reserved bit.
A priority level of 0 to 7 can be set for IRQ2.
Reserved bit.
A priority level of 0 to 7 can be set for SPI
slave.
Reserved bit.
A priority level of 0 to 7 can be set for I
slave.
ADuC7060
2
2
C
C