EVAL-ADUC7060QSPZ Analog Devices Inc, EVAL-ADUC7060QSPZ Datasheet - Page 53

• Manufacturer Part Number: EVAL-ADUC7060QSPZ
• Description: Quick Start Development System
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ PLUS Kitr
• Type: MCU, ARM7r

Specifications of EVAL-ADUC7060QSPZ

• Contents: Evaluation Board, Power Supply, Cable, Software, Emulator and Documentation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC7060
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q5189809

NONVOLATILE FLASH/EE MEMORY
The ADuC7060 incorporates Flash/EE memory technology
on-chip to provide the user with nonvolatile, in-circuit reprogram-
mable memory space.
Like EEPROM, flash memory can be programmed in-system
at a byte level, although it must first be erased. The erase is
performed in page blocks. As a result, flash memory is often
and, more correctly, referred to as Flash/EE memory.
Overall, Flash/EE memory represents a step closer to the
ideal memory device that includes nonvolatility, in-circuit
programmability, high density, and low cost. Incorporated in
the ADuC7060, Flash/EE memory technology allows the user
to update program code space in-circuit, without the need to
replace one time programmable (OTP) devices at remote
operating nodes.
The ADuC7060 contains a 64 kB array of Flash/EE memory.
The lower 62 kB are available to the user and the upper 2 kB
contain permanently embedded firmware, allowing in-circuit
serial download. These 2 kB of embedded firmware also contain
a power-on configuration routine that downloads factory-
calibrated coefficients to the various calibrated peripherals
(such as ADC, temperature sensor, and band gap references).
This 2 kB embedded firmware is hidden from user code.
FLASH/EE MEMORY RELIABILITY
The Flash/EE memory arrays on the parts are fully qualified for
two key Flash/EE memory characteristics: Flash/EE memory
cycling endurance and Flash/EE memory data retention.
Endurance quantifies the ability of the Flash/EE memory to be
cycled through many program, read, and erase cycles. A single
endurance cycle is composed of four independent, sequential
events, defined as
•
•
•
•
In reliability qualification, every half word (16-bit wide)
location of the three pages (top, middle, and bottom) in the
Flash/EE memory is cycled 10,000 times from 0x0000 to
0xFFFF. The Flash/EE memory endurance qualification is
carried out in accordance with JEDEC Retention Lifetime
Specification A117 over the industrial temperature range of
−40°C to +125°C. The results allow the specification of a
minimum endurance figure over a supply temperature of
10,000 cycles.
Initial page erase sequence
Read/verify sequence a single Flash/EE
Byte program sequence memory
Second read/verify sequence endurance cycle
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Retention quantifies the ability of the Flash/EE memory to
retain its programmed data over time. Again, the parts are
qualified in accordance with the formal JEDEC Retention
Lifetime Specification A117 at a specific junction temperature
(T
EE memory is cycled to its specified endurance limit, described
previously, before data retention is characterized. This means
that the Flash/EE memory is guaranteed to retain its data for its
fully specified retention lifetime every time the Flash/EE
memory is reprogrammed. Also note that retention lifetime,
based on activation energy of 0.6 eV, derates with T
Figure 21.
PROGRAMMING
The 62 kB of Flash/EE memory can be programmed in-circuit,
using the serial download mode or the provided JTAG mode.
Serial Downloading (In-Circuit Programming)
The ADuC7060 facilitates code download via the standard
UART serial port. The parts enter serial download mode after a
reset or power cycle if the NTRST/BM pin is pulled low
through an external 1 kΩ resistor. When in serial download
mode, the user can download code to the full 62 kB of Flash/EE
memory while the device is in-circuit in its target application
hardware. An executable PC serial download is provided as part
of the development system for serial downloading via the UART.
JTAG Access
The JTAG protocol uses the on-chip JTAG interface to facilitate
code download and debug.
J
= 85°C). As part of this qualification procedure, the Flash/
600
450
300
150
0
30
Figure 21. Flash/EE Memory Data Retention
40
JUNCTION TEMPERATURE (°C)
55
70
85
100
125
ADuC7060
135
J
as shown in
150