EVAL-ADUC7060QSPZ Analog Devices Inc, EVAL-ADUC7060QSPZ Datasheet - Page 79

• Manufacturer Part Number: EVAL-ADUC7060QSPZ
• Description: Quick Start Development System
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ PLUS Kitr
• Type: MCU, ARM7r

Specifications of EVAL-ADUC7060QSPZ

• Contents: Evaluation Board, Power Supply, Cable, Software, Emulator and Documentation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC7060
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q5189809

UART Status Register 1
COMSTA1 Register
Name:
Address:
Default value:
Access:
Function:
Table 90. COMSTA1 MMR Bit Descriptions
Bit
7:5
4
3:1
0
UART Interrupt Enable Register 0
COMIEN0 Register
Name:
Address:
Default value:
Access:
Function:
Name
CTS
DCTS
Description
Reserved. Not used.
Clear to send.
Reserved. Not used.
Delta CTS.
Set automatically if CTS changed state since
COMSTA1 was last read.
Cleared automatically by reading COMSTA1.
COMSTA1
0xFFFF0718
0x00
Read only
COMIEN0
0xFFFF0704
0x00
Read and write
The 8-bit register enables and disables the
individual UART interrupt sources.
COMSTA1 is a modem status register.
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Table 91. COMIEN0 MMR Bit Designations
Bit
7:4
3
2
1
0
UART Interrupt Identification Register 0
COMIID0 Register
Name:
Address:
Default value:
Access:
Function:
Name
EDSSI
ELSI
ETBEI
ERBFI
COMIID0
0xFFFF0708
0x01
Read only
This 8-bit register reflects the source of the
UART interrupt.
Description
Reserved. Not used.
Modem status interrupt enable bit.
Set by user to enable generation of an
interrupt if any of COMSTA1[3:1] are set.
Cleared by user.
Receive status interrupt enable bit.
Set by user to enable generation of an
interrupt if any of the COMSTA0[3:1] register
bits are set.
Cleared by user.
Enable transmit buffer empty interrupt.
Set by user to enable an interrupt when the
buffer is empty during a transmission; that is,
when COMSTA[5] is set.
Cleared by user.
Enable receive buffer full interrupt.
Set by user to enable an interrupt when the
buffer is full during a reception.
Cleared by user.
ADuC7060