EVAL-ADUC7060QSPZ Analog Devices Inc, EVAL-ADUC7060QSPZ Datasheet - Page 59

• Manufacturer Part Number: EVAL-ADUC7060QSPZ
• Description: Quick Start Development System
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ PLUS Kitr
• Type: MCU, ARM7r

Specifications of EVAL-ADUC7060QSPZ

• Contents: Evaluation Board, Power Supply, Cable, Software, Emulator and Documentation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC7060
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q5189809

FIQSTAN
If IRQCONN.1 is asserted and FIQVEC is read, then one of
these bits asserts. The bit that asserts depends on the priority of
the FIQ. If the FIQ is of Priority 0 then Bit 0 asserts, Priority 1
then Bit 1 asserts, and so forth.
When a bit is set in this register, all interrupts of that priority
and lower are blocked.
To clear a bit in this register, all bits of a higher priority must be
cleared first. It is possible to clear only one bit as a time. For
example, if this register is set to 0x09 then writing 0xFF changes
the register to 0x08 and writing 0xFF a second time changes the
register to 0x00.
FIQSTAN Register
Name:
Address:
Default value:
Access:
Table 73. FIQSTAN MMR Bit Designations
Bit
31:8
7:0
Table 74. IRQCONE MMR Bit Designations
Bit
31:8
7:6
5:4
3:2
1:0
Name
Reserved
Value
11
10
01
00
11
10
01
00
11
10
01
00
11
10
01
00
FIQSTAN
0xFFFF013C
0x00000000
Read and write
Description
These bits are reserved and should not be
written to.
Setting this bit to 1 enables nesting of FIQ
interrupts. Clearing this bit means no nesting
or prioritization of FIQs is allowed.
Name
Reserved
IRQ3SRC[1:0]
IRQ2SRC[1:0]
IRQ1SRC[1:0]
IRQ0SRC[1:0]
Description
These bits are reserved and should not be written to.
External IRQ3 triggers on falling edge.
External IRQ3 triggers on rising edge.
External IRQ3 triggers on low level.
External IRQ3 triggers on high level.
External IRQ2 triggers on falling edge.
External IRQ2 triggers on rising edge.
External IRQ2 triggers on low level.
External IRQ2 triggers on high level.
External IRQ1 triggers on falling edge.
External IRQ1 triggers on rising edge.
External IRQ1 triggers on low level.
External IRQ1 triggers on high level.
External IRQ0 triggers on falling edge.
External IRQ0 triggers on rising edge.
External IRQ0 triggers on low level.
External IRQ0 triggers on high level.
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External Interrupts (IRQ0 to IRQ3)
The ADuC7060 provides up to four external interrupt sources.
These external interrupts can be individually configured as level
or rising/falling edge triggered.
To enable the external interrupt source, first of all, the appropriate
bit must be set in the FIQEN or IRQEN register. To select the
required edge or level to trigger on, the IRQCONE register
must be appropriately configured.
To properly clear an edge based external IRQ interrupt, set the
appropriate bit in theIRQCLRE register.
IRQCONE Register
Name:
Address:
Default value:
Access:
IRQCONE
0xFFFF0034
0x00000000
Read and write
ADuC7060